用于特征提取的小尺寸事件型卷积处理器
发布时间：2018-11-20 21:39
【摘要】：设计了一款用于动态视觉传感器数据特征提取的小尺寸事件型卷积处理器,该卷积处理器包含了32×32的累加阵列、用于存储卷积核的RAM阵列、左/右移位模块、控制模块和异步的事件读出模块。为了减小面积,设计了2 bit的32×32的RAM阵列来存储所需的卷积核;在累加阵列中,采用7 bit的二进制计数器代替传统的加法器来实现卷积核的累加操作,在0.18μm CMOS工艺下,每个卷积单元的面积为37.5μm×40μm,对于每个事件输入输出的最小延时为17 ns,能够处理的最大事件率为12.5 Meps。基于该卷积处理器搭建了一个识别系统,利用16个卷积处理器来提取特征,利用脉冲神经网络实现了分类识别。实验结果表明,使用2 bit卷积核的小尺寸卷积处理器能够准确完成对输入事件的卷积操作,而且基于该卷积处理器所搭建的识别系统对MNIST数据库的识别效率可以达到90.57%。
[Abstract]:A small event type convolution processor for feature extraction of dynamic visual sensor data is designed. The processor consists of 32 脳 32 accumulative arrays, RAM arrays for storing convolutional cores and left / right shift modules. Control module and asynchronous event readout module. In order to reduce the area, a 32 脳 32 RAM array of 2 bit is designed to store the required convolution cores. In the accumulative array, 7 bit binary counter is used instead of the traditional adder to realize the accumulative operation of the convolution kernel. In 0.18 渭 m CMOS process, the area of each convolution unit is 37.5 渭 m 脳 40 渭 m. Minimum delay of 17 ns, per event I / O maximum event rate of 12.5 Meps. Based on the convolution processor, a recognition system is built, 16 convolution processors are used to extract the features, and a pulse neural network is used to realize classification recognition. The experimental results show that the small size convolution processor using 2 bit convolution core can accurately complete the convolution operation of input events, and the recognition system based on this convolution processor can recognize the MNIST database with an efficiency of 90.57.
【作者单位】： 天津大学电子信息工程学院;
【分类号】：TN47
本文编号：2346117
[Abstract]:A small event type convolution processor for feature extraction of dynamic visual sensor data is designed. The processor consists of 32 脳 32 accumulative arrays, RAM arrays for storing convolutional cores and left / right shift modules. Control module and asynchronous event readout module. In order to reduce the area, a 32 脳 32 RAM array of 2 bit is designed to store the required convolution cores. In the accumulative array, 7 bit binary counter is used instead of the traditional adder to realize the accumulative operation of the convolution kernel. In 0.18 渭 m CMOS process, the area of each convolution unit is 37.5 渭 m 脳 40 渭 m. Minimum delay of 17 ns, per event I / O maximum event rate of 12.5 Meps. Based on the convolution processor, a recognition system is built, 16 convolution processors are used to extract the features, and a pulse neural network is used to realize classification recognition. The experimental results show that the small size convolution processor using 2 bit convolution core can accurately complete the convolution operation of input events, and the recognition system based on this convolution processor can recognize the MNIST database with an efficiency of 90.57.
【作者单位】： 天津大学电子信息工程学院;
【分类号】：TN47
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