LHC ALICE电磁量能器点对点读出电子学研究
发布时间：2021-08-01 16:41
2018年后,大型强子对撞机（Large Hadron Collider, LHC）会逐渐增加Pb束流的亮度, Pb-Pb相互作用率最终会增加至50kHz左右。该事件率是目前大型重离子碰撞实验（A Large Ion Collision Experiment, ALICE）上电磁量能器（Electromagnetic Calorimeter, EMCal）事件读出率的20倍。另外,在2009年末新批准的ALICE双喷注电磁量能器（Di-jet Calorimeter, DCal）对读出电子学的要求与EMCal探测器相同,并计划于2013-2014年LHC停机期间安装至LHC上。因此,在2013-2014年停机前将EMCal探测器读出电子学的死时间降低到20胪是本文工作的主要目标。为了满足以上物理实验的两个升级计划的要求,本文结合EMCal/DCal探测器物理数据的特点,深入分析了EMCal/DCal探测器原有读出系统的读出链路,发现了系统瓶颈,并通过以下方案将EMCal探测器读出电子学的死时间从400μs降低到了19μs:1)通过FPGA固件升级,利用稀疏读出算法,将读出电子学的死时间...
【文章来源】：华中师范大学湖北省 211工程院校 教育部直属院校
【文章页数】：129 页
【学位级别】：博士
【文章目录】：
摘要
Abstract
List of Figures
List of Tables
Chapter 1 Introduction
1.1 Large Hadron Collider
1.2 A Large Ion Collsion Experiment
1.3 ALICE detectors
1.3.1 Electromagnetic Calorimeter
1.3.2 Di-jet Calorimeter
Chapter 2 Readout Electronics of the EMCal Detector
2.1 Detection principle
2.2 Architecture of the Readout Electronics
2.3 Preamplifier and Shaper
2.4 Signal digitization and Data compression
2.5 Data formatting
Chapter 3 Sparse Readout and Time Analysis for the Present GTL Bus based Readout
3.1 The topology of the existing GTL bus based readout system
3.2 The event size and occupancy of the EMCal detector
3.3 The readout timing and maximum event readout rate
3.4 Sparse Readout
Chapter 4 Time Analysis of the new Point-to-Point Readout
4.1 The Topology of the Point-to-Point Readout
4.2 The timing and maximum event readout rate
4.3 Low gain channel readout suppression
4.4 Use of Ten Gigabit Ethernet
Chapter 5 Hardware Design for the Point-to-Point Readout Prototype
5.1 Introduction
5.2 Hardware Design of the SRU board
5.2.1 Introduction
5.2.2 SRU Power and Heat Dissipation Investigation
5.2.3 Multi-boot circuit
5.2.4 TTCrx interface
5.3 Hardware Design of the DTC daughter card
5.3.1 Introduction
5.3.2 Power switch circuit
5.3.3 DTC clock transmission
Chapter 6 Firmware Design for the Point-to-Point Readout Prototype
6.1 Firmware architecture
6.2 Synchronization of the DTC interfaces
6.3 SRU Detector Control Network
6.3.1 SRU DCS in ALICE Online System
6.3.2 SRU DCS Concept
6.3.3 Error detection and reporting
6.3.4 SRU configuration module
6.3.5 DTC master module
6.3.6 Flash controller
6.3.7 DCS Frame
6.4 SRU Trigger handling
6.4.1 Trigger sequence and timing
6.4.2 Trigger error detection and reporting method
6.4.3 Software Triggers for Event Synchronization
6.5 Data acquistion concept
6.5.1 Data Acquisition Chain
6.5.2 Event Readout Process and Multi-event Buffer Management
6.5.3 Readout BUSY handling
6.6 Transactions over DDL link
6.6.1 User defined front-end control transaction
6.6.2 User defined front-end status word read-out transaction
6.6.3 DIU control transaction
6.6.4 SIU control transaction
6.6.5 Interface status read-out transaction
6.6.6 Event data transmission transaction
6.6.7 User defined data block downloading transaction
6.6.8 User defined data block read transaction
6.6.9 Self-test transaction
6.7 Remote Firmware Upgrade Through Ethernet
6.7.1 Motivation
6.7.2 Implementation concept
6.7.3 Hardware and Software Implementation
6.8 Plateau Test of the DTC Link
6.9 Event Readout Rate Test Performace
Chapter7 Conclusion and outlook
Appendices
1 TTC interface and connection
2 TTC trigger error reporting
3 TTCrx trigger data format
3.1 TTC broadcast command
3.2 TTC individual addressed command
3.3 Trigger messages
4 TTCrx internal register
5 LTU Setup
6 TTC timing
6.1 TTC trigger message
6.2 TTC test sequence timing
7 Firmware use of the SRU Boot Code
8 Flash Test
9 Flash access interface
10 ARP and ICMP packets captured through Wireshark
11 DTC Frame Format
12 SRU(SIU) DDL Frame Generator
13 Rorc receiver loading
Bibliography
Publication list
Acknowledgements
本文编号：3315875
【文章来源】：华中师范大学湖北省 211工程院校 教育部直属院校
【文章页数】：129 页
【学位级别】：博士
【文章目录】：
摘要
Abstract
List of Figures
List of Tables
Chapter 1 Introduction
1.1 Large Hadron Collider
1.2 A Large Ion Collsion Experiment
1.3 ALICE detectors
1.3.1 Electromagnetic Calorimeter
1.3.2 Di-jet Calorimeter
Chapter 2 Readout Electronics of the EMCal Detector
2.1 Detection principle
2.2 Architecture of the Readout Electronics
2.3 Preamplifier and Shaper
2.4 Signal digitization and Data compression
2.5 Data formatting
Chapter 3 Sparse Readout and Time Analysis for the Present GTL Bus based Readout
3.1 The topology of the existing GTL bus based readout system
3.2 The event size and occupancy of the EMCal detector
3.3 The readout timing and maximum event readout rate
3.4 Sparse Readout
Chapter 4 Time Analysis of the new Point-to-Point Readout
4.1 The Topology of the Point-to-Point Readout
4.2 The timing and maximum event readout rate
4.3 Low gain channel readout suppression
4.4 Use of Ten Gigabit Ethernet
Chapter 5 Hardware Design for the Point-to-Point Readout Prototype
5.1 Introduction
5.2 Hardware Design of the SRU board
5.2.1 Introduction
5.2.2 SRU Power and Heat Dissipation Investigation
5.2.3 Multi-boot circuit
5.2.4 TTCrx interface
5.3 Hardware Design of the DTC daughter card
5.3.1 Introduction
5.3.2 Power switch circuit
5.3.3 DTC clock transmission
Chapter 6 Firmware Design for the Point-to-Point Readout Prototype
6.1 Firmware architecture
6.2 Synchronization of the DTC interfaces
6.3 SRU Detector Control Network
6.3.1 SRU DCS in ALICE Online System
6.3.2 SRU DCS Concept
6.3.3 Error detection and reporting
6.3.4 SRU configuration module
6.3.5 DTC master module
6.3.6 Flash controller
6.3.7 DCS Frame
6.4 SRU Trigger handling
6.4.1 Trigger sequence and timing
6.4.2 Trigger error detection and reporting method
6.4.3 Software Triggers for Event Synchronization
6.5 Data acquistion concept
6.5.1 Data Acquisition Chain
6.5.2 Event Readout Process and Multi-event Buffer Management
6.5.3 Readout BUSY handling
6.6 Transactions over DDL link
6.6.1 User defined front-end control transaction
6.6.2 User defined front-end status word read-out transaction
6.6.3 DIU control transaction
6.6.4 SIU control transaction
6.6.5 Interface status read-out transaction
6.6.6 Event data transmission transaction
6.6.7 User defined data block downloading transaction
6.6.8 User defined data block read transaction
6.6.9 Self-test transaction
6.7 Remote Firmware Upgrade Through Ethernet
6.7.1 Motivation
6.7.2 Implementation concept
6.7.3 Hardware and Software Implementation
6.8 Plateau Test of the DTC Link
6.9 Event Readout Rate Test Performace
Chapter7 Conclusion and outlook
Appendices
1 TTC interface and connection
2 TTC trigger error reporting
3 TTCrx trigger data format
3.1 TTC broadcast command
3.2 TTC individual addressed command
3.3 Trigger messages
4 TTCrx internal register
5 LTU Setup
6 TTC timing
6.1 TTC trigger message
6.2 TTC test sequence timing
7 Firmware use of the SRU Boot Code
8 Flash Test
9 Flash access interface
10 ARP and ICMP packets captured through Wireshark
11 DTC Frame Format
12 SRU(SIU) DDL Frame Generator
13 Rorc receiver loading
Bibliography
Publication list
Acknowledgements
本文编号：3315875
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