基于逐次逼近结构的高速低功耗模数转换器研究

发布时间：2018-01-02 09:34

本文关键词：基于逐次逼近结构的高速低功耗模数转换器研究　出处：《东南大学》2017年博士论文　论文类型：学位论文

【摘要】：随着无线通信、便携式测试仪器等方面的快速发展,要求模数转换器(ADC)的速度越来越高、功耗越来越低。逐次逼近型(SAR)ADC拥有固有的结构简单、面积小、功耗低等特性,工艺特征尺寸的不断降低使得SAR ADC具有了实现高速转换的可能性,而移动通信、物联网、消费电子的飞速发展,对高速低功耗ADC也提出了很大的需求。所以研究以逐次逼近结构为基础的高速低功耗ADC对高速低功耗的应用领域具有非常重要的意义。本课题对单核SAR ADC的设计进行了深入的研究,对进一步降低SAR ADC的功耗和提高SAR ADC转换速度的关键技术进行了探讨。本文研究的主要内容如下:1、本文对SAR ADC中低功耗DAC开关电容阵列进行了深入研究,提出了一种低功耗的基于Vcm的分离电容阵列结构。该结构通过将最高位电容分离为1组二进制权重的电容阵列,以及采用终端匹配电容与Vcm相结合产生最低位量化所需的参考电压的技术,减少了 DAC电容阵列所需的单位电容个数和平均充放电功耗,提高了 DAC的速度。和传统的结构相比,基于Vcm的分离电容阵列结构所需的单位电容个数减少了 75%,功耗降低了 93.7%,建立速度提高了 25%,同时还使得DAC输出共模电平基本保持不变,减小了比较器输入端的动态失调。采用所提出的基于Vcm的分离电容阵列结构,在90nm CMOS工艺下设计了 10位SAR ADC,并对其中的逻辑控制电路模块进行了优化设计,缩短了逻辑控制电路的延迟,提高了 SAR ADC的转换速度。仿真结果表明,该ADC采样速率可达150MS/s,有效位数为9.9位,功耗为2.2mW。2、为了进一步提高SAR ADC的转换速度,本文对DAC模块的速度优化技术进行了研究。分析和讨论了采用冗余补偿技术缩短DAC建立时间的方法,提出了一种基于二进制冗余补偿及分离电容技术的分段结构DAC。通过二进制冗余补偿技术,降低了 DAC建立精度的需求,缩短了 DAC的建立时间;通过分离电容技术减小了 DAC建立时间常数,提高了 DAC的建立速度。在12位SAR ADC中,与传统分段结构DAC相比,提出的DAC的总的建立时间减少了 55%,速度提高了 1倍。基于提出的高速DAC结构,在0.18μm CMOS工艺下实现了一款12位高速SAR ADC。测试结果表明,该ADC的最高转换速率可达 100MS/s,SNDR 为 59dB,功耗为 6.2mW。3、针对SAR ADC中DAC电容阵列的电容失配导致的非线性问题,本文研究了 DAC电容阵列中电容失配的校正技术,提出了一种基于低位电容阵列复用的数字域自校正技术。该技术通过复用低位段电容阵列作为校正DAC,在ADC开始正常转换之前,对高位段电容阵列电容从高到低逐位的进行失配误差检测和量化,并将误差码存储起来。正常转换开始后,将输出的原始码与误差码求和获得最终的输出。为了解决失配误差估计过程中所需要的比较器的失调电压校正,本文对在两级动态比较器的第一级和第二级分别引入额外的负载不平衡电容补偿失调电压的方法进行了对比分析,发现在第一级实现失调电压补偿的方法更有优势。利用这一分析结果,提出了一种基于负载电容补偿的失调校正电路,使得比较器的失调电压减小到1LSB以内,满足了系统的精度要求。基于提出的数字域自校正技术设计了一款12位SARADC,并在40nm CMOS工艺下进行了电路级仿真。仿真结果表明,提出的数字域自校正技术有效的减小了电容失配对SAR ADC性能的影响。4、本文对低功耗的双电容阵列DAC进行了研究,提出了改进型双电容阵列DAC。与传统结构相比,改进后的双电容阵列DAC在功耗和面积上分别减少了 99.3%和71.9%。本文还对两级动态比较器结构进行了研究,提出了改进的两级动态比较器结构,通过增加锁存器作为第一级的负载,提高比较器的增益,从而进一步提高比较器的速度。
[Abstract]:With the rapid development of wireless communication, portable instrument and other aspects of the requirements of analog-to-digital converter (ADC) has become more and more high, more and more low power consumption. The successive approximation (SAR) ADC has inherent structure simple, small size, low power consumption characteristics, to reduce the feature size of the SAR ADC has the possibility of achieving high speed conversion, and mobile communications, networking, rapid development of consumer electronics, a great demand for high speed and low power ADC is proposed. So the research to the successive approximation applications of high speed low power ADC structure based on high speed and low power consumption has very important significance. The design of the single core SAR ADC this topic conducted in-depth research, to further reduce the power consumption of SAR ADC and discusses the key technology to improve the SAR ADC conversion rate. The main contents of this paper are as follows: 1, the SAR ADC low power DAC Close the capacitor array is studied, proposes a low power isolation capacitor array structure based on Vcm. The structure by high capacitance capacitor array is separated into 1 groups of binary weights, and the use of terminal matching capacitor combined with Vcm to generate the reference voltage required for quantification of low technology, reduced by DAC capacitor array required unit capacitor number and average charge and discharge power, improve the speed of DAC. Compared with the traditional structure, the number of unit capacitors separating capacitor array structure of Vcm based on the desired reduced by 75%, power consumption is reduced by 93.7%, a rate increased by 25%, while also making the DAC output common mode level of basic remain unchanged, reduce the input of the dynamic comparator disorders. By separating the capacitor array structure based on Vcm proposed by 90nm CMOS in the process design of 10 SAR ADC, and the control logic The circuit module is optimized, the logic control circuit to shorten the delay, improve the SAR ADC conversion speed. The simulation results show that the ADC sampling rate up to 150MS/s, 9.9 effective digits, power consumption is 2.2mW.2, in order to further improve the SAR ADC conversion speed, the speed of DAC module on the optimization technology study. Analyzed and discussed using redundancy compensation technology to shorten the time of establishing the DAC method, the paper proposes a segmentation structure of DAC. binary redundancy compensation and capacitor separation technology based on binary through redundancy compensation technology, reduces the DAC requirement, shorten the DAC setup time; by separating the capacitor technology reduces the DAC time constant to improve the speed of DAC, was established. In 12 SAR ADC, and the traditional segmental structure compared to DAC, DAC proposed the total build time reduced by 55%, speed 1 times higher. High speed DAC structure based on 0.18 m CMOS technology to achieve a 12 bit high speed SAR ADC. test results show that the highest conversion rate of up to 100MS/s ADC, SNDR 59dB, power consumption of 6.2mW.3, aiming at the nonlinear capacitance of DAC capacitor array SAR in ADC due to the mismatch problem is studied in this paper. The capacitor mismatch correction DAC capacitor array, this paper presents a self calibration technique of digital domain multiplexing based on low capacitance array. The technique by multiplexing the low section capacitor array as the calibration DAC, before the start of the normal conversion in ADC, the peak of capacitor array capacitance from high to low by a mismatch error detection and quantization, and error code stored. Normal conversion after the start of the original code output and error codes and obtain the final output. In order to solve the mismatch error estimation of offset comparator needed in Piezoelectric The correction in the two stage dynamic comparator is the first level and second level respectively introduce additional load balancing method of capacitance compensation offset voltage was analyzed, found in the first level implementation advantage offset voltage compensation method. The results of this analysis, propose an offset correction circuit load capacitance compensation based on the offset voltage of the comparator is reduced to less than 1LSB, to meet the requirements of the accuracy of the system. Design of a 12 bit SARADC digital domain is proposed based on self correction, and the circuit level simulation in 40nm CMOS process. The simulation results show that the proposed digital self-tuning technology effectively reduces the influence of the.4 capacitor mismatch on the performance of ADC SAR, the DAC of low power dual capacitor array is studied, put forward the improved double capacitor array DAC. compared with the traditional structure, the improved double capacitor array Column DAC in power and area were reduced by 99.3% and 71.9%. the two level dynamic comparator structure was studied, this paper proposes two level dynamic comparator with improved structure, by increasing the latch as the first level load, improve the comparator gain, so as to further improve the speed of the comparator.

【学位授予单位】：东南大学
【学位级别】：博士
【学位授予年份】：2017
【分类号】：TN792

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