集成电路新型ESD防护器件研究

发布时间：2018-01-06 15:18

本文关键词：集成电路新型ESD防护器件研究　出处：《浙江大学》2016年博士论文　论文类型：学位论文

【摘要】：集成电路的ESD (Electrostatic Discharge)防护设计是提高集成电路和电子系统可靠性的重要关键技术。本文分析了集成电路ESD防护设计及其应用背景,提出了新颖的ESD防护器件,满足了应用领域新技术的要求,并借助理论分析和TCAD (Technology Computer Aided Design)仿真设计研究了器件的工作机理,对有关结果进行流片实验和测试验证。具体研究内容和创新点如下：1.提出了基于0.35μm CMOS工艺的新型GGISCR (Gate-Grounded-nMOS Incorporated Silicon Controlled Rectifier)器件,相比目前通用的LVTSCR (Low Voltage Triggered Silicon Controlled Rectifier)器件,在不增加器件面积、不降低器件鲁棒性的前提下可将维持电压提升到7.9V,40μm宽度的GGISCR器件的失效电流达到4.4A,解决了传统ESD防护器件在器件面积、鲁棒性和维持电压三者之间折中矛盾的关键难题。论文借助使用TCAD仿真工具,研究了器件在ESD应力下的直观重要物理量,包括：电场、电流密度和碰撞离化率等,结合上述结果对其工作机制进行分析和阐述。有关结果发表在TED期刊,并申请发明专利。2.提出了基于0.35μm 40V BCD (Bipolar CMOS DMOS)工艺的改进型GGISCR器件,通过优化器件结构和并联小尺寸GGLDMOS (gate-grounded Lateral Double-diffused MOS)器件,完整地验证了其ESD防护的有效性,该设计成功应用于某上市公司的电源管理芯片的电源钳位单元。主要的创新点是基于BCD工艺的特点进一步缩小了器件的回滞窗口,失效电流达到3.5A。通过堆叠的方式极大地提高了器件的维持电压,解决了电源钳位单元存在的闩锁问题,满足18V和24V电源应用,技术指标优越。3.设计了一种新型ESD防护器件FP-LDMOS-SCR (Floating P+Lateral Double-diffused MOS Silicon Controlled Rectifier)器件,用于0.35μm 40V BCD工艺I/O接口的ESD防护。通过在LDMOS器件漏端设计浮空P+区,将器件的失效电流提升到2.7A,且不影响器件正常工作的I-V特性。FP-LDMOS-SCR器件提升了高压I/O接口的ESD鲁棒性且降低了闩锁风险。有关结果发表在MR期刊。4.在0.35μm 80V BCD工艺平台上设计了LDMOS-SCR器件,解决了传统LDMOS器件在ESD应力下出现过早失效的关键难题。TLP测得LDMOS-SCR器件失效电流值为4.3A。通过在漏端插入一个场氧结构,将LDMOS-SCR器件的击穿电压从92V提升到99V,进一步增强了器件耐压特性。5.设计了具有超高鲁棒性的ESD防护器件,其失效电流高达18.9A,满足IEC61000-4-2 15KV接触放电的ESD防护等级。主要的创新点是在对GGISCR器件的失效机理分析的基础上,设计了高效的圆形版图器件,其FOM(Figure of Merit)值为137AV/pF,比常规的多指条型版图性能提升73%,技术指标远优于目前业界的主流产品,有关结果已申请发明专利。6.设计了一种新型的穿通型五层N++P+PP+N++结构的TVS (Transient Voltage Suppressor)器件。其十二指条型器件获得超过10A的失效电流,不大于0.17pF的寄生电容,解决了传统TVS器件寄生电容过大影响系统信号完整性的问题,满足诸如USB3.0和HDMI1.4高速接口的系统级ESD防护应用,技术指标远优于目前业界的主流产品。有关结果投稿IEEJ期刊(已录用),并申请发明专利。
[Abstract]:Integrated circuit ESD (Electrostatic Discharge) is a key technique to improve protection design reliability of integrated circuit and electronic system. This paper analyzes the design of integrated circuit ESD protection and its application background, put forward the ESD protection device novel, meet new application technical requirements, and by means of theoretical analysis and TCAD (Technology Computer Aided Design) simulation design studies the working mechanism of the device, carried out experiments and tests to verify the results. The specific contents are as follows: 1. novel GGISCR 0.35 m based on CMOS Technology (Gate-Grounded-nMOS Incorporated Silicon Controlled Rectifier) device, compared to the current general LVTSCR (Low Voltage Triggered Silicon Controlled Rectifier) device. Without increasing device area, robustness under the premise of the device will maintain the voltage up to 7. is not reduced 9V, the failure of current GGISCR device 40 m width up to 4.4A, to solve the traditional ESD protection devices in the device area, the key problem of compromise the contradiction between robustness and maintain the voltage of three. With the use of TCAD simulation tools, on the device under stress directly important physical quantities in ESD include: electric field. The current density and the impact ionization rate, combined with the results of its work mechanism is described and analyzed. The results were published in the Journal TED, the invention patent.2. proposed 0.35 m 40V based on BCD (Bipolar CMOS DMOS) and the application of improved GGISCR device technology, through the optimization of device structure and parallel small size GGLDMOS (gate-grounded Lateral Double-diffused MOS devices), to validate the effectiveness of ESD protection, the power management chip design is successfully applied to a listed company in the power clamp unit. The main innovations are based The characteristics of BCD technology in further reducing the device hysteresis window, failure current reaches 3.5A. by stacking method greatly improves the device to maintain the voltage, solve the existing power clamp unit latch, meet the requirements of 18V and 24V power applications, technical superiority index.3. design of a new type of ESD protection device FP-LDMOS-SCR (Floating P+Lateral Double-diffused MOS Silicon Controlled Rectifier) devices, ESD protection for 0.35 m 40V BCD process I/O interface. Through the design of floating drain area of P+ on the LDMOS device, the device failure current up to 2.7A, the I-V characteristics of.FP-LDMOS-SCR devices and does not affect the normal working of the device to enhance the robustness of ESD high voltage I/O interface and reduce the latch risk. Relevant results published in the MR Journal.4. 0.35 m 80V BCD technology platform is designed to solve the traditional LDMOS-SCR devices, LDMOS devices in ESD Under the.TLP key problem of premature failure of the measured current value of 4.3A. LDMOS-SCR device failure through the drain into a field oxide structure, the breakdown voltage of LDMOS-SCR devices increased from 92V to 99V, to further enhance the breakdown voltage characteristics of.5. design with ESD protection device of high robustness, high current failure up to 18.9A, to meet the ESD protection grade IEC61000-4-2 15KV contact discharge. The main innovation is the basis of analysis on the failure mechanism of GGISCR devices on the design of the circular layout device with high efficiency, the FOM (Figure of Merit) is 137AV/ pF, a 73% more than the conventional lifting type layout performance, technical index is far better than the current mainstream products in the industry, the relevant results have been applied to a new five layer through the N++P+PP+N++ structure of TVS.6. (Transient Voltage design patent Suppressor). The twelve refers to the device type A failure current is more than 10A, not more than the parasitic capacitance of 0.17pF, to solve the traditional TVS devices too large parasitic capacitance effect system of signal integrity, meet system level ESD protection applications such as USB3.0 and HDMI1.4 high speed interface, technical index is far better than the current mainstream industry products. The results contribute IEEJ Journal (accepted), and apply for a patent.

【学位授予单位】：浙江大学
【学位级别】：博士
【学位授予年份】：2016
【分类号】：TN40

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