集成电路工艺偏差的片上检测与应用

发布时间：2018-01-28 01:27

本文关键词： 工艺偏差片上检测电容阵列测量时域放大器时序参数测量物理不可克隆散列函数　出处：《浙江大学》2016年博士论文　论文类型：学位论文

【摘要】：随着半导体工业的发展,工艺的特征尺寸不断缩小,芯片的集成度不断提高,集成电路设计和制造的复杂度也不断增大。当器件的特征尺寸进入纳米尺度后,工艺偏差对器件性能带来很大影响,严重制约了集成电路的性能、功耗和成品率等。工艺偏差的检测技术是半导体工艺领域的一个研究热点,它依赖于参数测量技术。静态参数和时序参数是表征工艺偏差的两个要素。通过片上参数的提取,可以分析芯片内部工艺偏差的分布、建立相关模型、修改完善工艺步骤,从而降低工艺偏差,加快新工艺的开发进度。工艺偏差的随机性可能给芯片带来难以预料的后果,而在信息安全领域,工艺偏差的随机性却具有很高的应用价值。工艺偏差是集成电路制造过程的必然产物,其随机性来源于制造过程中固有的各种不可控因素。通过工艺偏差相关参数的提取,可以形成每个芯片独特的参数标识,从而为日益普及的智能终端的身份识别等提供一个有效的解决方案。本文围绕集成电路工艺偏差的片上检测与应用展开了以下几方面的研究:1.首先提出一种全新的片上电容阵列测量方法,实现集成电路片上电容参数的大规模高精度测量,从而实现对片上电容偏差的检测。工艺偏差检测对样本数量和测量精度有很高要求。片上电容阵列测量方法通过层次化的系统结构设计,利用电容阵列测量单元和多路模拟通道选择单元,实现少量芯片面积开销下的大规模高精度电容检测。电容阵列测量单元采用基于充放电的电容测量方法,在精确的信号控制下确保电容测量精度符合需求。本文在180纳米的CMOS工艺下实现了片上电容阵列测量的原型芯片。芯片的测量结果显示,电容测量精度达到1fF。本文还给出了芯片电容偏差的分布情况,并对影响电容测量结果的相关因素进行分析和比较。片上电容阵列测量方法所采用的系统层次结构可以很容易地推广到其他静态参数的片上检测,具有很强的灵活性和通用性。2.在静态参数片上检测的研究基础上,进一步提出一种全新的片上高精度时序参数测量方法,解决片外电学测量方法无法实现高精度时序参数测量的问题。时序参数对静态参数作用于时序信号后所产生的响应,包括信号上升沿时间、下降沿时间和传输延时等。片上高精度时序参数测量方法采用全新的结合等效时间采样和实时采样的测量结构,实现信号时序信息皮秒精度的片上检测。时域放大器是实现等效时间采样的主要单元,其在采样信号的控制下实现对待测波形信号在时域上的放大,然后通过对放大后的波形进行过采样、滤波和模数转换等操作,生成最终的数据信息。本文在180纳米的CMOS工艺下实现了片上高精度时序参数测量的原型芯片。从芯片的测量结果中可以得出高精度实测边沿波形,从波形中可以得到精确的边沿时间偏差分布。本文利用片上高精度时序参数测量方法,首次测得触发器建立时间和保持时间的偏差分布情况。3.通过工艺偏差片上检测技术的研究和工艺偏差相关特性的分析,本文提出一种全新的物理不可克隆散列函数的概念。物理不可克隆散列函数是基于硬件实现的散列函数,它利用工艺偏差的随机性来实现散列映射。参照算法加密散列函数的相关运算和多轮散列操作,物理不可克隆散列函数可以根据任意长度的输入激励生成固定长度的输出响应,从而利用有限的资源开销生成无穷多的激励-响应对,使其在实际应用中的安全性得到极大的提高。本文在180纳米的CMOS工艺下实现了物理不可克隆散列函数的原型芯片。通过芯片的测量和评估,对物理不可克隆散列函数的独特性、可靠性和散列映射中的抗碰撞性进行分析。物理不可克隆散列函数还具有无法复制、难以实现逆向破解等特性,使其在信息安全应用中具备了很强的竞争力。
[Abstract]:With the development of semiconductor industry, technology feature size shrinking, chip integration continues to improve, integrated circuit design and manufacturing complexity is also increasing. When the feature size of the device into the nano scale, process variations have great influence on the performance of the device, seriously restrict the performance of an integrated circuit, power consumption and rate of finished products. Detection technology. The deviation is a hot research field of semiconductor technology, it relies on the measurement of parameters. The static parameters and timing parameters are two factors characterizing process deviation. Through the parameter extraction, can analyze the distribution of chip process variation, establish related model, revise and improve the process steps, thereby to reduce process variation, accelerate the development of new technology progress. Random process variations may bring to chip There's no telling the consequences, and in the field of information security, process deviation The randomness has very high application value. The deviation is the inevitable product of integrated circuit manufacturing process, the various sources of randomness inherent in the manufacturing process of uncontrollable factors. Through the extraction process deviation related parameters, parameter identification of each chip can form a unique, so as to provide an effective solution for intelligent the growing popularity of the terminal identification. This paper focuses on the integrated circuit process deviation on chip detection and application of the following aspects: 1. first proposed a new on-chip capacitor array measurement method, high precision measurement of large-scale integrated circuit chip capacitor parameters, so as to realize the detection of Capacitance Deviation on chip the process deviation detection of sample quantity and the measurement accuracy is very high. The system structure design of capacitor array measurement sheet through the hierarchy, using capacitor array The measurement unit and the analog channel selection unit, to achieve large-scale high-precision capacitance detect small chip area overhead. The capacitor array measuring unit uses capacitance measurement method based on charge and discharge, the control signal under accurate capacitance to ensure measurement accuracy meets the requirements. This paper implements a prototype chip capacitor array measurement on a sheet of CMOS 180 nanometer process under the chip measurement results showed that the capacitance measurement accuracy of 1fF. the distribution of chip capacitance deviation is given, and the related factors affecting the capacitance measurement results were analyzed and compared. The hierarchical structure of on-chip capacitor array measurement method can be easily extended to other static parameters on chip detection basic research, with strong flexibility and versatility of.2. detection in static parameters on chip, proposed a new on-chip high Method of measuring accuracy of timing parameters, solve the method of electrical measurement chip can be realization of high precision timing measurement. Response timing parameters on the static parameters in the timing signal generated by the signal, including the rise time, fall time and transmission delay. The high precision timing parameter measurement method based on equivalent time sampling based on chip the structure and measurement of real time sampling new, detect signal timing information of picosecond precision on chip. The time domain is the main amplifier unit to realize equivalent time sampling, the control of the sample signal to be amplified under the measured waveform signal in the time domain, and then through the enlarged waveform sampling, filtering and analog-to-digital conversion operation, to generate the final data. This paper implements a prototype chip high precision timing parameters on a sheet of CMOS 180 nanometer process chip from. The measurement results can be obtained in the high accuracy edge waveform, waveform can be obtained from the edge of time deviation distribution accurately. Using high precision timing parameter measurement method on the measurement and analysis for the first time to trigger setup time and hold time deviation distribution of.3. through the research and process deviation detection technology process deviation on the related the characteristics, the paper puts forward the concept of a new physical unclonable hash function. Physical unclonable hash function is a hash function based on hardware, it uses random process deviation to achieve hash mapping. Correlation algorithm according to cryptographic hash functions and multiple hash operations, physical unclonable hash function according to the arbitrary length of the input output of fixed length response, thereby generating an infinite number of incentive to response with limited resource overhead, The safety in the practical application has been greatly improved. This paper implements a prototype chip physical unclonable hash function in CMOS 180 nanometer process. Through the measurement and evaluation of the chip, the unique physical unclonable hash function, collision resistance and reliability analysis of hash mappings. Physical unclonable hash function has not copy, it is difficult to achieve reverse break and other characteristics, the application of information security has very strong competitive power.

【学位授予单位】：浙江大学
【学位级别】：博士
【学位授予年份】：2016
【分类号】：TN407

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