基于40纳米硅基CMOS工艺的60 GHz锁相环研究

发布时间：2018-02-09 12:23

本文关键词： 锁相环 60 GHz CMOS VCO　出处：《浙江大学》2017年博士论文　论文类型：学位论文

【摘要】：在过去的半个世纪以来,整个人类社会的生活方式已经被无线通信技术的急速发展所彻底改变。锁相环(Phase-LockedLoop)是无线收发机中射频前端电路的关键模块。本论文基于国内设计、国内制造和国内测试,实现了首款完全国产化的40 nm硅基CMOS工艺的60 GHz锁相环芯片,其功耗、相噪等主要性能指标及FOM优值均达到国际先进水平,这对提升我国高端射频芯片国产化的能力具有积极作用和贡献。论文的主要工作和创新点如下。(1)60GHz射频工艺模型的研究。目前国内工艺厂商无法提供用于电磁场分析的ADS库。本论文在互连线趋肤效应的研究基础上,成功利用“路分析”的方法在只有20GHz能力的国内工艺线上实现了这款芯片的国产化。所以本论文首先进行了射频传输性能的研究以及建立了相应的SPICE仿真模型。(2)60GHz锁相环芯片的设计实现。与国内大多数射频IC设计人员多选择国外加工工艺不同,本论文立足国内40 nm CMOS工艺线,设计并首次实现了一款性能理想的60 GHz锁相环芯片,相位噪声达到-92dBc/Hz@1 MHz、-110 dBc/Hz@10MHz,FOM为-170.7dB。这是基于国内自主工艺线实现的工作频率最高、性能最好的锁相环芯片。(3)更高性能VCO的研究。因我国射频IC设计研究起步较晚,为了追赶国际同行的步伐,本论文还进一步研究了几种更高性能60 GHz压控振荡器(VCO)的创新技术,从低功耗、抗PVT涨落(即工艺离散、电源电压波动、温度变化)、低相位噪声三个方面分别尝试突破,并在40 nm工艺线上对该三种VCO进行了流片验证:低功耗VCO在1.2V电源电压下消耗了 10.4mW的功率。与对照实验的传统VCO相比,在相位噪声性能不受影响的情况下,功耗降低了 23.5%。抗PVT涨落的VCO与作为对照的传统VCO相比,代表了工艺离散的6组芯片在不同电源电压下的输出信号功率平均偏差降低了 1.8 dBm,同时优值FOM 也从-165 dB 提高到-169 dB。低相位噪声技术的VCO,其相位噪声达到-85dBc/Hz@1MHz。与对照组的传统VCO相比,相位噪声降低了 4 dB。但是,此项技术的代价是功耗也有了相应增加,所以FOM优值没有改善。
[Abstract]:In the past half century, the way of life of the whole human society has been completely changed by the rapid development of wireless communication technology. Phase-Locked Loop (PLL) is the key module of RF front-end circuit in wireless transceiver. The 60 GHz PLL chip of the first completely domestic 40 nm silicon-based CMOS process has been realized by domestic manufacture and domestic testing. Its power consumption, phase noise and other main performance indexes, as well as the excellent value of FOM, have reached the international advanced level. The main work and innovation of this paper are as follows: the research on RF process model of 1GZ is as follows. At present, the domestic manufacturers can not provide the technology for electromagnetic field separation. The main work and innovation of this paper are as follows: (1) the main work and innovation of this paper are as follows: 1 / 1 / 60GHz RF process model. This paper is based on the study of the skin effect of interconnection lines. The method of "path analysis" has been successfully used to realize the localization of this chip on the domestic process line with only 20GHz capability. In this paper, the RF transmission performance is studied and the corresponding SPICE simulation model is established. The design and realization of PLL chip is different from that of most RF IC designers at home and abroad. Based on the domestic 40nm CMOS process line, a 60 GHz PLL chip with ideal performance is designed and implemented for the first time. The phase noise reaches -92 dBc / Hzr / HzR 1MHz / 10dBc / Hz10MHz / 10dBc / Hz10MHz FOM = -170.7dB.This is the highest working frequency based on the domestic independent process line. In order to catch up with the international counterparts, this paper also further studies several innovative techniques of 60 GHz VCOs with higher performance, due to the late start of RF IC design research in China. From the aspects of low power consumption, resisting PVT fluctuation (i.e. process discretization, voltage fluctuation of power supply, temperature change and low phase noise), we try to break through each other. The three kinds of VCO are verified on the 40nm process line. The low-power VCO consumes 10.4mW of power at 1.2V power supply voltage. Compared with the conventional VCO in the control experiment, the phase noise performance is not affected. The power consumption is reduced by 23.5. the VCO that resists the fluctuation of PVT is compared with the traditional VCO which is used as a control. It represents that the average output power deviation of six groups of chips with discrete process at different power supply voltages is reduced by 1.8 dBms. at the same time, the excellent value of FOM is increased from -165dB to -169dB.The phase noise of low phase noise technology is -85dBc / HzBZ 1MHz. Compared to the traditional VCO, The phase noise is reduced by 4 dB. However, the cost of this technique is the corresponding increase in power consumption, so the FOM value is not improved.
【学位授予单位】：浙江大学
【学位级别】：博士
【学位授予年份】：2017
【分类号】：TN911.8

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