面向星载一体化综合电子系统的固态存储技术研究

发布时间：2018-02-12 07:22

本文关键词： 星载固态存储器 NAND Flash ASIC 高速并行缓存即插即用 SoC FPGA刷新与重加载 RS码、LDPC码、级联编码　出处：《中国科学院国家空间科学中心》2017年博士论文　论文类型：学位论文

【摘要】：星载固态存储系统作为卫星综合电子系统的关键组成部分,完成对卫星数据处理和数据记录等功能。随着卫星任务向着复杂化和多样化发展,面临以下两方面问题:一方面,现有星载固态存储系统方案设计高度定制化,灵活性差,缺乏可扩展性和可配置性,并且未实现即插即用设计;另一方面由于西方国家严格限制高性能的宇航级和军品级电子元器件对我国的出口,核心、高端和基础元器件国产化水平低,自主研发的进程较慢,致使国内星载固态存储系统整体性能偏低。在此背景下,以现有基于FPGA平台的固态存储控制技术为出发点,针对固态存储技术在一体化综合电子系统中的应用,在通用化、集成化和高可靠性等方面完成以下研究工作:首先,提出了星载固态存储控制器ASIC的设计方案。能够完成对高速、多路并行和大数据量的航天器载荷数据的合路接收、对大容量NAND Flash存储介质的高效控制以及按照CCSDS AOS协议对数据进行复接传输功能。为提高数据传输效率,在虚拟信道调度机制上采用基于紧张度的改进型轮询仲裁机制和多通道高速缓存技术。为具备可扩展性和通用性,采用星上通用1553B总线和SpaceWire总线接口。在系统级应用中,以ASIC为控制核心,实现存储板的标准化和即插即用功能,并在未来星载存储系统中完成对FPGA器件的替代。其次,以下一代抗辐照龙芯处理器SoC升级移植和拓展NAND Flash存储介质应用为目标,提出了基于NAND Flash的固态存储控制器IP核设计。在完成常规数据存储功能的同时,具备对SRAM型FPGA刷新和重加载控制的功能。通过对存储介质接口的时序转换,星载计算机能够对存储介质内全部空间进行读写访问,完成卫星在轨更新FPGA配置文件的功能,并在星载电子系统中实现了NAND Flash对NOR Flash和E2PROM的替代。最后,由于空间环境中单粒子翻转效应(Single Event Upset,SEU),以及存储器芯片在操作过程中因阈值电压偏移导致位比特错误等原因,使得存储数据的可靠性降低。为提高数据存储系统的数据容错性,依据NAND型Flash芯片物理结构和数据存储结构,针对性的提出一种RS(256,252)码+LDPC(8192,7154)码级联的纠检错(Error Detection And Correction,EDAC)并行编码设计,并优化编码算法的电路实现,在有限的硬件资源开销下,提高了整个存储系统的数据可靠性。
[Abstract]:Spaceborne solid-state storage system, as a key component of satellite integrated electronic system, performs the functions of satellite data processing and data recording. With the development of satellite mission towards complexity and diversification, it faces the following two problems: on the one hand, The design of the existing space-borne solid-state storage system is highly customized, with poor flexibility, lack of scalability and configuration, and no plug and play design. On the other hand, because western countries strictly restrict the export of high performance aerospace grade and military grade electronic components to our country, the level of localization of core, high-end and basic components is low, and the process of independent research and development is relatively slow. Under this background, the solid state storage control technology based on FPGA platform is taken as the starting point, aiming at the application of solid state storage technology in integrated electronic system. The following research work has been done in the aspects of integration and high reliability: firstly, a design scheme of spaceborne solid state storage controller (ASIC) is proposed, which can receive the payload data of high speed, multichannel parallel and large amount of data. The efficient control of large capacity NAND Flash storage medium and the function of multiplexing data according to CCSDS AOS protocol. In the virtual channel scheduling mechanism, the improved polling arbitration mechanism based on tension and the multi-channel cache technology are adopted. In order to be extensible and versatile, the on-board universal 1553B bus and SpaceWire bus interface are used. With ASIC as the control core, the function of standardization and plug and play of memory board is realized, and the replacement of FPGA device in the future space-borne memory system is completed. Secondly, Aiming at upgrading, transplanting and expanding the application of NAND Flash storage medium in the next generation of irradiation-resistant core processor (SoC), the IP core design of solid-state storage controller based on NAND Flash is proposed. It has the function of refreshing and reloading the SRAM type FPGA. Through the timing conversion of the storage medium interface, the spaceborne computer can read and write all the space in the storage medium and complete the function of updating the FPGA configuration file in the satellite orbit. The substitution of NOR Flash and E2PROM by NAND Flash is realized in the spaceborne electronic system. Finally, because of the single Event upsetSEUU effect in the space environment and the bit bit error caused by the threshold voltage deviation in the operation of the memory chip, and so on. In order to improve the data tolerance of data storage system, according to the physical structure and data storage structure of NAND type Flash chip, This paper presents a parallel coding design of error Detection And Correction (EDACC) concatenated in RSH256F252) LDPC-8192 / 7154) code, and optimizes the circuit implementation of the coding algorithm. Under the limited hardware resource overhead, the data reliability of the whole storage system is improved.
【学位授予单位】：中国科学院国家空间科学中心
【学位级别】：博士
【学位授予年份】：2017
【分类号】：V443;TP333

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