深纳米CMOS技术寄生效应及其波动性的精准模型与参数提取研究

发布时间：2018-05-08 07:48

本文选题：深纳米CMOS工艺 + 寄生效应波动性　；参考：《华东师范大学》2016年博士论文

【摘要】：CMOS工艺特征尺寸的等比例减小使得器件尺寸、接触孔边长与间距、互连线线宽与间距缩小至深纳米数量级,进而导致MOS器件栅结构周围、多层互连线的寄生电容与电阻等寄生效应日趋严重,器件栅围和互连线的寄生效应所产生的延时远远超过了器件的本征延时,对高速电路设计中时序分析、功耗分析、信号完整性设计等带来了巨大挑战。因此,准确描述CMOS工艺的各种寄生效应及其波动性、并实现深纳米电路仿真的精准模型至关重要。本论文以深纳米工艺代CMOS技术所产生的寄生效应及其波动性为研究对象,意图深入分析并建立前端MOSFET非本征栅围寄生电容模型、栅电阻模型及与工艺波动相关的后端多层互连线寄生电容和电阻模型。论文工作中自主设计并制造了深纳米工艺代的寄生电容与电阻测试结构,建立了基于电学数据(Silicon Data)的模型建立和参数提取流程,自主实现了SPICE模型和互连线工艺格式(Interconnect Technology Format, ITF)文件的扩充和优化。基于上述目标,本论文的工作可以概括为以下四项：一、针对MOSFET非本征部分的栅围寄生电容,本论文基于40nm CMOS工艺,重点研究了多晶硅栅至接触孔距离(Contact to Poly Space,缩写CPS)、接触孔至接触孔距离(Contact to Contact Space,缩写CCS)变化对栅至源/漏边缘电容Cf及其波动性的影响。工作中,自主设计并流片制备了25个CCS和CPS尺寸的Gate-Poly测试结构及Field-Poly去嵌结构。分析测试所得电学数据表明,Cf的波动具有较明显的版图布局相关性,在CPS和CCS接近设计规则允许的最小尺寸下有将近200%的波动。通过对电学数据的分析,本论文建立了Cf版图布局效应的SPICE模型与参数提取流程,对电学数据达到了5%的拟合,并且对模型进行了准确的验证。二、针对MOSFET栅围寄生电阻,本论文基于40nm CMOS工艺,提出了多晶硅栅电阻的模型拓扑结构,重点研究了多晶硅栅电阻的非线性效应的模型,包括温度与偏压特性、寄生电容特性。工作中,通过42个不同尺寸的N+、P+开尔文(Kelvin)栅电阻测试结构的电学数据,对温度相关特性(Temperature-Dependent Characteristics, TDC)、温度相关的偏压次级效应TDVC (Temperature-Dependent Voltage Characteristics)、以及栅与衬底耦合寄生电容进行了准确建模和参数提取。三、针对多层互连工艺,本论文重点研究了化学机械抛光(Chemical Mechanical Polish, CMP)、光学邻近修正(Optical Proximity Correction, OPC)等工艺波动对寄生效应的影响,本文基于55nm l P4M工艺自主设计了1种在片(On Wafer)测试电路、3类模型测试结构、1类模型校准结构。其中,在片测试电路基于CIEF CBCM测试方法(Charge-injection-induced Error-free Charge-based Capacitance Measurement),由不交叠的信号驱动进行两步测量,扣除了测试电路中的寄生参量,使测试精度到达0.1fF级别,待测电容面积缩小至传统大面积电容结构的1/160。模型测试结构和校准结构包括：1、不同线宽(Width)和线间距(Space)的同层金属互连线耦合寄生电容测试结构。2、不同Width和Space的层间金属互连线覆盖寄生电容测试结构。3、不同Width和不同Space的多层金属寄生电容校准结构。4、不同Width和Space的单层四端开尔文金属互连线寄生电阻测试结构。四、针对多层互连工艺,不同于器件效应的SPICE建模,本论文建立版图寄生参数(Layout Parasitic Extraction, LPE)流程,通过完善反应局部波动性的典型(Typical)文件和反应全局波动性的角(Corner) ITF文件,对互连工艺寄生效应进行建模。在对典型ITF校准中,通过比对测试所得的电学数据,代工厂所提供的基础典型ITF的电容与电阻提取值误差十分明显,同层金属互连线耦合寄生电容误差普遍超过20%,最大误差达到60%；层间金属互连线覆盖寄生电容误差普遍在5%-15%之间；同层金属互连线寄生电阻误差普遍在20%-50%之间。为了减少典型ITF的提取误差,本文建立基于电学数据的典型ITF文件完善流程,使得最终典型ITF文件的所有待测结构提取值与电学数据误差小于5%。在对工艺角(Corner)ITF的校准中,校准全局互连线及电介质层形变波动的3G,使测试值区间位于提取值范围之间。本文工作所得到的典型ITF与角ITF提取精度及范围均符合半导体产业技术要求。本文基于国有深纳米工艺平台,自主建立并完善了深纳米CMOS工艺寄生效应波动性的模型及参数提取流程,取得突出成果如下：I、自主设计了40nm工艺的栅围寄生电容Cf待测结构与去嵌结构,创造性的提出了Cf版图布局效应,并自主建立了相应的SPICE模型和参数提取流程,能够在电路仿真中准确的评估MOSFET栅围寄生电容的版图布局效应对器件的影响。取得工作成果发表于SCI检索期刊Solid-State Electronics。2、自主创建了40nm工艺的多晶硅栅电阻的温度与偏压特性建模流程,描述了多晶硅栅电阻的非线性效应,建立的SPICE模型能够准确的评估多晶硅栅电阻在电路中的影响。取得工作成果发表于EI检索会议International Conference on Engineering Technology and Application (2015)。3、自主设计了55nm工艺的金属互连线测试结构和测试电路,创建了基于电学数据的ITF矩阵单元调整策略和参数提取流程,完善了典型ITF以及角ITF文件。本工作最终完善的ITF不仅仅提取精度达到产业界要求,同时对后道互连工艺参数调整和高端芯片后端布局布线都有重要的指导意义。取得工作成果发表于SCI检索期刊IEEE Electron Devices Letters。
[Abstract]:The equal proportion of the characteristic size of the CMOS process reduces the size of the device, the length and the distance of the contact hole, the line width and spacing of the interconnect line to the deep nanoscale order of magnitude, and then the parasitic effects of the parasitic capacitance and resistance of the multi-layer interconnects are becoming increasingly serious, and the delay of the parasitism of the gate and interconnects in the MOS device is caused by the increase of the line width and spacing of the interconnect lines. Far more than the intrinsic delay of the device, it has brought great challenges to the timing analysis, power analysis and signal integrity design in high speed circuit design. Therefore, it is very important to accurately describe the various parasitic effects and the volatility of the CMOS process, and to realize the precise model of the deep nanoscale circuit simulation. This paper uses the deep nano technology to replace the CMOS technology. The parasitic effect and its fluctuation are studied. The purpose of this study is to analyze and establish the front MOSFET non eigengate parasitic capacitance model, the gate resistance model and the parasitic capacitance and resistance model of the back-end multilayer interconnects, which are related to the process fluctuation. The model building and parameter extraction process based on electrical data (Silicon Data) are established and the SPICE model and the interconnect process format (Interconnect Technology Format, ITF) file are expanded and optimized independently. Based on the above objectives, the work of this paper can be summarized as following four items: 1, non intrinsic to MOSFET Part of the gate enclosure parasitic capacitance, based on the 40nm CMOS process, this paper focuses on the study of the influence of the distance between the polysilicon gate to the contact hole distance (Contact to Poly Space, abbreviated CPS), the contact hole to the contact hole distance (Contact to Contact Space, abbreviated CCS) changes on the gate to source / leakage edge capacitance and its fluctuation. 25 CCS and CPS size Gate-Poly test structures and Field-Poly inlay structures. Analysis and test electrical data show that Cf fluctuations have a more obvious layout correlation, and there are nearly 200% fluctuations in the minimum size allowed by the design rules of the CPS and CCS. Through the analysis of the electrical data, the paper establishes the Cf Edition The SPICE model and parameter extraction process of the local effect are fitted to 5% of the electrical data, and the model is verified accurately. Two, based on the MOSFET grid parasitic resistance, the model topology of the polysilicon gate resistance is proposed based on the 40nm CMOS process, and the nonlinear effect model of the polysilicon gate resistance is focused on. Including temperature and bias characteristics, parasitic capacitance characteristics. In work, electrical data of 42 different sizes of N+, P+ Kelvin (Kelvin) gate resistance test structure, temperature dependent properties (Temperature-Dependent Characteristics, TDC), temperature dependent bias voltage secondary effect TDVC (Temperature-Dependent Voltage Characteristics), Accurate modeling and parameter extraction of the coupling parasitic capacitance between the gate and the substrate. Three, in this paper, the effects of Chemical Mechanical Polish (CMP), optical proximity correction (Optical Proximity Correction, OPC) on parasitic effects are studied in this paper, based on the 55nm L P4M process. The main design of 1 On Wafer test circuit, 3 type of model test structure, 1 class model calibration structure, in which the chip test circuit based on the CIEF CBCM test method (Charge-injection-induced Error-free Charge-based Capacitance Measurement), the non overlapping signal drive to carry out two steps, deducted the parasitism in the test circuit The test precision reaches the 0.1fF level, and the 1/160. model test structure and the calibration structure of the capacitance area to be reduced to the traditional large area capacitance structure include: 1, different Xian Kuan (Width) and line spacing (Space) of the same layer metal interconnect coupling parasitic capacitance test structure.2, the interlayer metal interconnects of different Width and Space cover parasitism. Capacitance test structure.3, different Width and different Space multi-layer metal parasitic capacitance calibration structure.4, different Width and Space single layer four terminal Kelvin metal interconnect parasitic resistance test structure. Four, for multi-layer interconnect process, different from the device effect of SPICE modeling, this paper establishes the layout parasitic parameters (Layout Parasitic Extraction,) LPE) process, modeling the parasitic effect of interconnect process by improving the typical (Typical) file and the global wave Corner ITF file that reacts the local volatility. In the typical ITF calibration, through the electrical data compared with the test, the error of the capacitance and resistance extraction value of the base typical ITF for the generation factory is very low. It is obvious that the parasitic capacitance error of the interconnect line of the same layer is generally more than 20% and the maximum error reaches 60%. The error of interlayer metal interconnect covering parasitic capacitance is generally between 5%-15%, and the parasitic resistance error of the interconnect line of the same layer is generally between 20%-50%. In order to reduce the extraction error of the typical ITF, this paper establishes the typical electrical data. The ITF file consummate the process, making the final typical ITF file of all the measured structure extraction value and electrical data error less than 5%. in the calibration of the process angle (Corner) ITF, calibrate the global interconnect and the dielectric layer deformation fluctuation 3G, make the test value interval between the extracted value range. The typical ITF and corner ITF extraction precision obtained in this work The degree and range are all in accordance with the technical requirements of the semiconductor industry. Based on the state-owned deep nano technology platform, the model and parameter extraction process of the parasitic effect of the deep nano CMOS process are established and perfected independently. The outstanding achievements are as follows: I, the design of the 40nm process of the grid parasitic capacitance Cf to be measured and inlaid structure, and the creativity of the structure are created independently. The layout effect of Cf layout is put forward, and the corresponding SPICE model and parameter extraction process are established independently. The effect of layout effect of MOSFET gate parasitic capacitance on the device can be accurately evaluated in the circuit simulation. The results of the work are published in the SCI retrieval Journal Solid-State Electronics.2, and the polycrystalline 40nm process is created independently. The modeling process of the temperature and bias characteristic of the silicon grid resistors describes the nonlinear effect of the polysilicon gate resistance. The SPICE model can accurately evaluate the influence of the polysilicon grid resistance in the circuit. The results are published in the EI retrieval conference International Conference on Engineering Technology and Application (2015).3, autonomous The metal interconnect test structure and test circuit of 55nm process are designed, the ITF matrix unit adjustment strategy and parameter extraction process based on electrical data are created, the typical ITF and the corner ITF files are perfected. The final perfect ITF not only achieves the industrial requirements, but also adjusts the technological parameters of the post channel interconnect and high end. The back-end layout and routing of chips has important guiding significance. The results obtained are published in the SCI search Journal IEEE Electron Devices Letters..

【学位授予单位】：华东师范大学
【学位级别】：博士
【学位授予年份】：2016
【分类号】：TN405

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