以数据为中心的多核处理器软硬件协同优化关键技术研究

发布时间：2018-05-17 01:10

本文选题：片上多核处理器 + 以数据为中心　；参考：《清华大学》2016年博士论文

【摘要】：未来的超大规模计算系统设计面临着两个很重要的挑战:能效性和以数据为中心的应用负载。片上多核处理器作为构成未来超大规模计算系统的基础之一,其设计和应用也需要向“低功耗高能效”和“以数据为中心“的需求转变。本文采用”以数据为中心“的设计思想,从片上多核处理器设计和应用的多个层面出发,使用软硬件协同优化设计的方法,以应用驱动设计,来提高片上多核处理器的能效性、并行扩展性和对不同应用的适应性。具体而言,在处理器内核层面,针对目标应用从计算和数据两个方面进行定制化设计和软硬件协同优化;在片上多核处理器多核互连层面,实现了硬件支持的片上消息传递机制;在片上多核处理器并行编程模式层面,针对不规则应用提出一种“计算趋近数据”的计算模式,提高了不规则应用在片上多核处理器上的计算性能和并行扩展性,并降低了功耗;最后,在多线程调度层面,提出了“以数据为中心”的推测多线程调度机制。本文的主要创新点包括:1.针对Stencil计算,采用将常规的软硬件优化手段跟基于目标应用定制设计相结合的思路,从一个简单可定制核开始,构建了一个低功耗高能效的处理内核。设计中使用了一系列软硬件结合的优化方法,提高了计算并行性和数据传输效率,减少了数据传输。2.针对片上多核处理器的片上消息传输机制设计了专门的消息引擎负责片上消息传递,并完成了消息引擎RTL级的实现。本文从减少数据无效复制、提高大消息传输效率、降低复杂通信开销三个方面对片上多核处理器的片上消息传输机制进行了优化。3.针对不规则应用在片上多核处理器上的执行瓶颈和挑战,提出In Place计算模式,实现计算向数据的趋近。通过减少数据在片上的移动,提高了处理器的执行效率;通过“划分”和“代理”机制避免了对不规则数据的竞争访问;通过构建“核间流水”提高了并行度和对带宽的利用。对于典型不规则应用在片上多核处理器上的执行,In Place模式提高了性能和并行扩展性,并降低了功耗。4.针对片上多核处理器单线程性能弱的问题,在片上多核处理器上实现了“兼容性”的推测多线程机制,能够利用片上空闲资源提升单线程能力。针对线程数据在片上多核处理器片上的不均匀分布,提出了“以数据为中心”的推测多线程调度机制,有效地提升了推测多线程机制在片上多核处理器上的执行效能。
[Abstract]:There are two important challenges to the design of large scale computing systems in the future: energy efficiency and data-centric application load. As one of the foundations of the future large scale computing system, the design and application of on-chip multi-core processors need to be changed to the requirements of "low power, high energy efficiency" and "data-centric". In this paper, we adopt the idea of "data as the center", proceed from the multi-level design and application of multi-core processors on a chip, use the method of hardware and software co-optimization design to improve the energy efficiency of multi-core processors on a chip by using the application-driven design. Parallel expansibility and adaptability to different applications. Specifically, at the processor kernel level, customization design and hardware / software co-optimization are carried out for the target application from two aspects of calculation and data. The mechanism of on-chip messaging supported by hardware is implemented, and a computing mode of "computing approaching data" is proposed for irregular applications at the level of parallel programming mode of multi-core processors on a chip. The computing performance and parallel expansibility of irregular applications on multi-core processors are improved, and the power consumption is reduced. Finally, at the multi-thread scheduling level, a "data-centric" speculated multithread scheduling mechanism is proposed. The main innovations of this paper include: 1. For Stencil computing, a low power and high energy efficient processing kernel is constructed by combining conventional software and hardware optimization methods with object-based application customization design, starting with a simple customizable kernel. In the design, a series of optimization methods combining software and hardware are used to improve the computing parallelism and data transmission efficiency, and reduce the data transmission. 2. A special message engine is designed to deliver message on a chip for the message transfer mechanism of multi-core processor on a chip, and the RTL level of message engine is implemented. This paper optimizes the on-chip message transmission mechanism of multi-core processors on a chip from three aspects: reducing invalid data replication, improving the efficiency of large message transmission, and reducing the complexity of communication overhead. Aiming at the bottleneck and challenge of irregular application in multi-core processor, in Place computing mode is proposed to realize the convergence of computing to data. By reducing the movement of data on the chip, the processor's execution efficiency is improved; the competing access to irregular data is avoided through "partitioning" and "proxy" mechanisms; and the parallelism and bandwidth utilization are improved by constructing "inter-core pipelining". For typical irregular applications in Place mode, the performance and parallelism are improved, and the power consumption is reduced. In order to solve the problem of low performance of single thread in multi-core processor on a chip, the "compatibility" mechanism of multi-thread is implemented on the chip, which can enhance the single-thread capability by using the free resources on the chip. Aiming at the uneven distribution of thread data on the multi-core processor chip, a data-centric scheduling mechanism is proposed, which effectively improves the performance of the speculated multi-thread mechanism on the multi-core processor.
【学位授予单位】：清华大学
【学位级别】：博士
【学位授予年份】：2016
【分类号】：TP332

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