静电放电及其防护器件研究

发布时间：2018-05-26 18:26

本文选题：ESD + 高压ESD防护　；参考：《湖南大学》2016年博士论文

【摘要】：静电放电(ESD)是造成集成电路失效的主要原因之一。研究ESD机理并采用适当有效的方法防止损害发生对集成电路的可靠性有重大影响。随着微电子行业的发展,集成电路的ESD保护面临越来越大的挑战。对集成电路的ESD可靠性进行研究,采取有效措施对集成电路芯片进行ESD保护,具有重要的理论意义和实际价值。本文对集成电路芯片内高压ESD保护器件进行深入研究。采用互补型和双扩散型(CDMOS)制造工艺,流片制备了三种不同形状的高压N沟道横向扩散MOS的ESD器件,采用传输线脉冲测试(TLP)系统测试器件的性能参数,结果显示,方型版图结构的电流能力比传统的叉指型和八角型分别增加30%和25%以上,具有高的鲁棒性,低的漏电流特性和高的电流放电效率。采用0.5微米5V/18VCDMOS工艺流片两组可控硅整流(SCR)ESD器件,使用TLP系统测试器件的性能参数,结果表明,LDMOS-SCRESD器件的维持电压随着N阱内P+区和P阱内N+区间距线性增大,而单位面积的失效电流线性减小。拟合维持电压和单位面积失效电流随间距变化的解析表达式,得到与实际一致的结果。采用软件仿真,获取单向LDMOS-SCRESD器件工作时I-V曲线,结果显示,器件的漂移区长度增加提高器件的失效电流但降低维持电压。提取关键点的少数载流子浓度、电流密度、电压强度等电学特性参数,分析得出内部载流子输运能力增强,但导通电阻无明显变化是该现象的内在原因。流片测试结果验证了仿真结果的正确性。双向高压DDSCR器件由两个单向SCR结构器件构成,研究发现DDSCR器件内对应于单向SCR结构器件漂移区的区域长度与器件性能有关。区域长度大,维持电压高,ESD保护水平降低;反之亦然。提出了一种新型的ESD保护器件(M-ESD器件),该器件内部忆阻器与寄生晶体管组成的系统能够有效地协同工作,在不增大芯片面积和不降低维持电压的情况下,使器件的失效电流增加,提高器件的保护水平。为了获得适合于M-ESD器件的忆阻元件,研究了纳米级器件Ag/MoSe2/Au的忆阻属性,采用水热法合成了MoSe2纳米样品,由光刻制作电极,器件显示出良好的双极电阻开关行为和较低的工作电压。本文对片外ESD保护压敏电阻进行了研究。提出了一种新型抗冲击老化的ZnO压敏陶瓷ESD器件,增加Pr_(0.1)Ca_(0.9)MnO_3陶瓷层,用于提高压敏电阻多次击穿后的抗老化能力。采用固相烧结方法制备了Pr_(1-x)Ca_xMnO_3(x=0.1)陶瓷样品,对样品在磁场和电场下直流、交流输运性质的研究表明,其电阻可分为晶粒体电阻与晶界电阻两部分,特性差异明显。同时测量了样品在不同频率下的阻抗温谱,拟合得出势垒高度与用直流R-T数据得出的激活能一致。提出一种新型抗寄生电容干扰的ZnO压敏ESD器件,制备了BiMnO_(3+δ)样品作为新型器件的忆阻材料,研究纳米级器件Ag/BiMnO_(3+δ)/Ag的忆阻属性。结果表明,Ag/BiMnO_(3+δ)/Ag器件的关/开电阻率达10,并且具有很好的稳定性。本文还对防静电材料进行研究,采用电化学沉积的方法,在铜衬底上制备一层硫化亚铜样品,在样品和铜衬底上溅射银电极,通过测试电输运特性研究硫化亚铜材料的忆阻特性,结果表明三明治结构的Ag/Cu_2S/Ag结构具有较高的忆阻效应,进一步利用该特性进行了防静电指示功能设计。
[Abstract]:Electrostatic discharge (ESD) is one of the main causes of the failure of integrated circuits. The study of the mechanism of ESD and the use of appropriate and effective methods to prevent the occurrence of damage have a significant impact on the reliability of integrated circuits. With the development of the microelectronics industry, the ESD protection of integrated circuits is facing more and more challenges. The reliability of the integrated circuits is studied, and the reliability of the integrated circuits is studied. It is of great theoretical significance and practical value to take effective measures for ESD protection of integrated circuit chips. In this paper, the high voltage ESD protection devices in integrated circuit chips are studied in depth. Using complementary and double diffusion (CDMOS) manufacturing technology, three kinds of ESD devices with different shapes of high voltage N channel transverse diffusion MOS are prepared. The transmission line pulse test (TLP) system is used to test the performance parameters of the device. The results show that the current capacity of the square pattern structure is increased by 30% and 25% more than the traditional interdigital and octagonal type. It has high robustness, low leakage current characteristics and high current discharge efficiency. 0.5 micron 5V/18VCDMOS process sheets are used to complete the silicon control. A flow (SCR) ESD device is used to test the performance parameters of the device using the TLP system. The results show that the maintenance voltage of the LDMOS-SCRESD device is linearly increased with the N+ zone spacing in the P+ region and the P well in the N well, and the failure current of the unit area is linearly reduced. The analytical expression of the fitting maintenance voltage and the unit area failure current with the distance is obtained. The result shows that the I-V curve of the unidirectional LDMOS-SCRESD device is obtained by software simulation. The result shows that the drift region length of the device is increased and the failure current of the device is increased, but the maintenance voltage is reduced. The parameters of the minority carrier concentration, current density and voltage intensity are extracted at the key point, and the internal carrier transport capacity is analyzed. The inner reason of the phenomenon is no obvious change in the conduction resistance. The flow test results verify the correctness of the simulation results. The bidirectional high voltage DDSCR device is composed of two unidirectional SCR structure devices. It is found that the length of the drift region corresponding to the unidirectional SCR structure device is related to the device performance. The length of the region is large and the dimension of the region is large. High voltage and lower ESD protection level, and vice versa. A new type of ESD protection device (M-ESD device) is proposed. The system composed of internal memristor and parasitic transistor can work effectively, increasing the failure current of the device without increasing the chip area and maintaining the maintenance voltage, and improving the protection of the device. In order to obtain the memristor elements suitable for M-ESD devices, the memristor properties of the nanoscale device Ag/MoSe2/Au are studied. The MoSe2 nano samples are synthesized by hydrothermal method. The electrodes are made by photolithography. The devices show good bipolar resistance switching behavior and low working voltage. This paper studies the ESD protective varistor in this paper. A new type of anti impact aging ZnO varistor ceramic ESD device was developed to increase the Pr_ (0.1) Ca_ (0.9) MnO_3 ceramic layer to improve the anti-aging ability of the varistor after multiple breakdown. A solid phase sintering method was used to prepare Pr_ (1-x) Ca_xMnO_3 (x=0.1) ceramics samples. The study on the AC transport properties of samples under magnetic field and electric field and the AC transport properties were studied. The resistance can be divided into two parts, grain resistance and grain boundary resistance. The characteristic difference is obvious. At the same time, the impedance temperature spectrum of the sample at different frequencies is measured. The height of the barrier is fitted to the activation energy obtained by the direct current R-T data. A new type of ZnO piezoelectric ESD device with a new anti parasitic capacitance interference is proposed, and the BiMnO_ (3+ delta) sample is prepared as a new sample. The memristor of the type device is used to study the memory resistance properties of the nano scale device Ag/BiMnO_ (3+ delta) /Ag. The results show that the close / open resistivity of Ag/BiMnO_ (3+ delta) /Ag device is 10 and has good stability. In this paper, the antistatic material was studied and a layer of copper sulfide samples was prepared on the copper substrate by electrochemical deposition. By sputtering the silver electrode on the copper substrate, the memristor characteristics of the copper sulfide materials are studied by measuring the electrical transport properties. The results show that the Ag/Cu_2S/Ag structure of the sandwich structure has a high recristor effect. Further use of this characteristic is used to design the anti static function.
【学位授予单位】：湖南大学
【学位级别】：博士
【学位授予年份】：2016
【分类号】：TN402

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