低功耗电荷重分配式CMOS逐次逼近型模数转换器研究

发布时间：2018-05-27 07:09

本文选题：模数转换器 + 逐次逼近　；参考：《西安电子科技大学》2016年博士论文

【摘要】：目前可穿戴设备、医学植入器件和无线传感网络等电池驱动设备越来越普及,但是电池容量却没有获得突破性进展,所以要求这些设备的功耗尽可能低,来延长它们的使用时间。作为这些设备的核心部件,模数转换器(Analog-to-Digital Converter,ADC)是连接模拟信号和数字信号的“桥梁”,所以其功耗也必须尽可能的低。在各类ADC中,逐次逼近型(Successive Approximation Register,SAR)ADC结构简单、模拟电路少、功耗低,并且随CMOS工艺的演进,功耗持续降低,所以SAR ADC是低功耗ADC的良好选择。SAR ADC中功耗最低的是电荷重分配结构,因为它并没有静态功耗,并且二进制搜索算法最有效,因此得到广泛应用。所以,本文重点研究了低功耗电荷重分配式SAR ADC的电容开关方法和相关电路实现。1.论文系统分析了SAR ADC的核心模块,包括数模转换器(Digital-to-Analog Converter,DAC)电容网络、采样开关、比较器和SAR控制逻辑。详细分析了几种典型DAC电容网络(传统结构、单调结构、基于共模电平VCM结构、三电平结构)的开关能量和线性;阐述了采样开关的两种实现方式,即传统MOS开关和栅压自举开关;分析了三种低功耗比较器,即单级动态比较器、两级全动态比较器和时域比较器;分析了SAR控制逻辑的三种实现方式,即静态SAR控制逻辑、半动态SAR控制逻辑和动态SAR控制逻辑。2.论文提出了四种低功耗DAC电容网络开关方法,包括两电平少开关结构、多电平结构、两电平高能效结构和三电平浮置电容结构。(1)两电平少开关结构开关方法基于单调结构开关方法,使用C-2C结构电容替换参考单位电容。与10位传统结构开关方法相比,其开关能量减少了90.61%,单位电容数量减少了74.7%,开关数量减少了41.18%。(2)多电平结构开关方法采用了5个参考电平(VREF,0.75VREF,VCM,0.25VREF和地),因为三电平一般需要电压基准产生电路,所以很容易产生5个电平。与10位传统结构开关方法相比,其开关能量减少了99.2%,单位电容数量减少了87.5%。(3)两电平高能效结构开关方法也是基于单调结构开关方法,重置序列为(0 1…1)而不是(1 1…1),参考单位电容通过两个C/2并联实现。与10位传统结构开关方法相比,其开关能量减少了95.31%,单位电容数量减少了74.7%。(4)三电平浮置电容结构开关方法使用浮置电容,实现从最小电容开始切换参考电平而不是从最大电容开始切换参考电平。与10位传统结构开关方法相比,其开关能量减少了99.6%,单位电容数量减少了87.21%。3.论文基于55 nm 1P7M 2.5 V CMOS工艺,设计了8位1.0 V 1-KS/s SAR ADC。提出了三电平DAC电容网络开关方法,其DAC输出电压共模电平和输入信号共模电平一致,在整个转换过程中不发生变化,与传统结构开关方法相比,开关能量减少了93.74%,单位电容数量减少了74.8%。为了降低漏电功耗,采用叠加CMOS结构实现采样开关,与同等沟道长度的非叠加CMOS开关相比,漏电流降低了将近一半。为了进一步降低功耗,比较器采用了纯锁存器构成的动态比较器,SAR控制逻辑采用了静态逻辑移位寄存器和动态逻辑锁存器实现的半动态SAR控制逻辑。流片测试结果显示,微分非线性(Differential Nonlinearity,DNL)误差为0.89/-0.64 LSB,积分非线性(Integral Nonlinearity,INL)误差为0.71/-0.97 LSB。在接近奈奎斯特输入信号频率、1.0 V电源电压情况下,该SAR ADC消耗7.9 n W,获得的ENOB为7.29位,FOM值为50.5 f J/conv.-step,芯片有效面积为160?270μm2。
[Abstract]:At present , battery - driven devices , such as wearable devices , medical implant devices , and wireless sensing networks , are becoming increasingly popular , but battery capacity has not achieved breakthrough progress , so the power consumption of these devices is required to be as low as possible to extend their use time . As a core component of these devices , Analog - to - Digital Converter ( ADC ) is a " bridge connecting analog signals and digital signals . This paper systematically analyzes the three kinds of realization modes of SAR ADC , namely static SAR control logic , semi - dynamic SAR control logic and dynamic SAR control logic , and analyzes three kinds of realization modes of SAR ADC , namely static SAR control logic , semi - dynamic SAR control logic and dynamic SAR control logic . Compared with the traditional structure switching method , the switching energy of the two - level structure is reduced by 90.61 % , the number of unit capacitors is reduced by 74.7 % , and the number of switches is reduced by 41.8 % . A three - level floating capacitor structure switching method uses floating capacitor to realize switching reference level from the minimum capacitance instead of starting to switch the reference level from the maximum capacitance . Compared with the traditional structure switching method , the switching energy is reduced by 99.6 % , and the number of unit capacitors is reduced by 74.21 % . In order to reduce the leakage power consumption , the output voltage of the converter is reduced by 74.8 % . In order to reduce the leakage power consumption , the output voltage of the converter is reduced by 74.8 % . In order to reduce the leakage power consumption , the comparator adopts a static logic shift register and a dynamic logic latch . In order to reduce the leakage power consumption , the value of ENOB is 7.29 bits . The effective area of the chip is 160 ? 270渭m2 .
【学位授予单位】：西安电子科技大学
【学位级别】：博士
【学位授予年份】：2016
【分类号】：TN792

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