薄膜晶体管器件在动态应力下的退化研究

发布时间：2018-05-30 10:04

本文选题：薄膜晶体管 + 低温多晶硅　；参考：《苏州大学》2016年博士论文

【摘要】：近几年来,以多晶硅或金属氧化物半导体为沟道材料的薄膜晶体管(TFTs)在面向高清电视和智能化、可触控式多媒体技术等新型平板显示产业中的应用而备受关注。目前,以低温多晶硅和铟镓锌氧(a-IGZO)为基础的TFT技术因为具有较高的迁移率和较低的工艺温度等优势已经成为新一代有源矩阵驱动的平板显示方案的重要研究方向。但是,TFTs的可靠性问题同样也限制着平板产业的进一步发展。在实际的工作电路中,TFTs不仅受到直流偏压的电应力而且还要承受着开关切换脉冲或信号变化等交流电信号的作用。相对而言,直流偏压的影响和作用的物理过程比较清楚,但交流脉冲下的退化现象及退化机制目前均没有统一的退化模型。因此,在本文中,我们分别研究了多晶硅TFTs和a-IGZO TFTs在各种动态应力下的退化现象,并提出了相应的退化机制。本文的主要研究内容和结果可概括如下:(一)多晶硅TFTs在动态应力下的退化在多晶硅TFTs的栅极施加脉冲电应力的作用下,通过改变栅脉冲的不同应力条件,具体研究了器件的退化与脉冲的上升沿、下降沿、脉冲个数、基准电压和平带电压的关系,在总结得出退化现象发生于脉冲的下降沿并取决于脉冲个数的基础上,提出非平衡态PN结退化模型。该退化模型阐述了器件从开态向关态的快速转换过程中,载流子从深能级缺陷发射出来后,受源/漏极附近高电场的作用之下,形成热载流子,并产生更多的缺陷,导致器件的性能退化。该模型能全面、完整地解释多晶硅TFTs在栅和漏极处分别施加脉冲应力或施加栅/漏同步脉冲应力所导致的器件退化现象。(二)一种含有载流子注入端的新型TFT及其退化抑制研究在理解退化发生过程的基础上,为提高TFTs的可靠性及驱动电路寿命,我们制备了一种可抑制动态退化的新型TFT,即通过在沟道一侧形成载流子注入端,载流子注入端的注入类型与源/漏导电类型相反。以新制备的n型器件为例,在脉冲下降沿切换时,载流子注入端注入的空穴可使沟道的载流子浓度跟得上栅极脉冲电压的变化速度,从而大幅抑制沟道源/漏区附近的非平衡态的形成以及热载流子的产生,达到抑制动态热载流子效应导致器件退化的目的。(三)a-IGZO TFTs的动态退化研究首先研究了最典型的栅极脉冲应力下a-IGZO TFTs器件的退化特性,比较了不同上升沿和下降沿对器件退化的影响关系。与多晶硅TFT类似的是,当栅脉冲的下降沿较陡时,器件性能的退化与动态热载流子导致的缺陷产生和电荷注入有关,且脉冲个数是导致退化的主要因素;当脉冲的下降沿较为平缓时,可以将脉冲的应力时间折算成“等效的直流应力时间”来衡量器件的退化行为,此时,栅脉冲的高电平时产生的电荷捕获是退化的主要原因,而动态热载流子效应的影响可忽略。根据实验现象,我们提出了由动态热载流子导致的器件退化模型,即在水平瞬态电场的作用下,沟道内来不及返回源、漏极的电子从水平瞬态电场中吸收能量成为热载流子,部分热载流子会越过界面势垒注入栅绝缘层或被界面捕获,导致的器件性能退化,并进一步借助于Silvaco仿真软件验证了提出退化模型的正确性。与栅脉冲下的动态退化不同的是,对于栅/漏同步脉冲应力和漏脉冲下的a-IGZO TFT器件退化,其本质上一个直流偏压导致的结果,它取决于脉冲的高电平时间长短,而与动态效应无关。特别需要指出的是,由于a-IGZO TFT存在着应力撤去后的恢复现象,导致a-IGZO TFT的最终退化量不仅取决直流等效应力,而且还与脉冲的低电平时间长短相关。此时,器件性能退化可归因于电应力作用下与热激发相关的电荷注入栅绝缘层或被界面捕获而产生的结果。
[Abstract]:In recent years, the thin film transistors (TFTs) with polysilicon or metal oxide semiconductors as channel materials have attracted much attention in the new type of flat display industry, such as high-definition television and intelligent, touchable multimedia technology. At present, the TFT technology based on low temperature polysilicon and indium gallium and zinc oxygen (a-IGZO) is high. The advantages of mobility and low process temperature have become an important research direction for the new generation of active matrix driven plate display scheme. However, the reliability of TFTs also restricts the further development of the flat industry. In the actual working circuit, TFTs is not only subjected to the electrical stress of the direct current bias but also to the switch. In contrast, the effects and physical processes of the DC bias are relatively clear, but there are no unified degradation models for the degradation and degradation mechanisms under the AC pulse. Therefore, in this paper, we studied the various dynamic responses of polysilicon TFTs and a-IGZO TFTs respectively. The main research contents and results in this paper can be summarized as follows: (1) the degradation of polysilicon TFTs under dynamic stress and pulse electrical stress exerted on the grid of polysilicon TFTs, the degradation and pulse of the device are studied by changing the different stress conditions of the gate pulse. The relation between the rising edge, the drop edge, the number of pulse, the voltage of the reference voltage and the voltage and the voltage of the reference voltage is presented. On the basis of the conclusion that the degenerate phenomenon occurs at the drop edge of the pulse and depends on the number of pulses, the degenerate model of the non-equilibrium PN junction is proposed. The degenerate model states that the carrier from the open state to the close state is a deep level defect. After being launched, under the action of high electric field near the source / drain, a hot carrier is formed and more defects are produced, resulting in the degradation of the performance of the device. This model can fully explain the phenomenon of device degradation caused by the application of pulse stress or gate / leakage synchronous pulse stress at the gate and leakage of polysilicon TFTs. (two) A new type of TFT and its degradation inhibition study containing the carrier injection end, based on the understanding of the degradation process, to improve the reliability of the TFTs and the life of the driving circuit, we have prepared a new type of TFT to suppress the dynamic degradation, namely, the carrier injection end on one side of the channel, the injection type of the carrier injection end and the leakage guide. The electric type is opposite. As an example of the newly prepared n type device, the hole injected into the carrier injection end can make the carrier concentration of the channel up to the change speed of the gate pulse voltage at the drop edge of the pulse, thus greatly restrains the formation of the nonequilibrium state near the channel source / leakage region and the generation of the hot carrier, so as to suppress the dynamic thermal load. The flow subtraction effect leads to the degradation of the devices. (three) the dynamic degradation of a-IGZO TFTs first studies the degradation characteristics of the a-IGZO TFTs devices under the most typical gate pulse stress, and compares the influence of the different rising and descending edges on the degradation of the devices. Similar to the polysilicon TFT, the performance of the device when the drop edge of the gate pulse is steep The degradation is related to the defect generation caused by the dynamic hot carrier and the charge injection, and the number of pulses is the main factor causing the degradation. When the drop edge of the pulse is relatively slow, the stress time of the pulse can be converted into "equivalent DC stress time" to measure the deionization behavior of the device, at this time, the high electricity generation of the gate pulse is produced. Charge capture is the main cause of degradation, and the effect of dynamic hot carrier effect can be ignored. According to the experimental phenomenon, we propose a device degradation model caused by dynamic hot carrier, that is, under the action of the horizontal transient electric field, the channel in the channel is not able to return to the source, and the leakage of the electric energy is absorbed from the horizontal transient electric field to become a thermal carrier. The partial heat carrier will cross the barrier barrier of the interface into the barrier layer or be captured by the interface, resulting in the degradation of the device performance, and the correctness of the degenerate model is verified by the Silvaco simulation software. Unlike the dynamic degradation under the gate pulse, the grid / leakage same step pulse stress and the a-IGZO TFT device under the leakage pulse are retreated. As a result of a DC bias in essence, it depends on the high level time of the pulse and has nothing to do with the dynamic effect. In particular, it is necessary to point out that the final degradation of the a-IGZO TFT depends not only on the equivalent stress of the direct current, but also with the low power of the pulse, as the a-IGZO TFT has a stress withdrawal. In this case, the performance degradation of the device can be attributed to the result of electric stress induced charge injection into the gate insulating layer or by the interface.
【学位授予单位】：苏州大学
【学位级别】：博士
【学位授予年份】：2016
【分类号】：TN321.5

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