非制冷红外焦平面探测器芯片一体化设计及关键技术研究

发布时间：2018-06-16 14:32

本文选题：红外焦平面探测器芯片 + 微测辐射热计　；参考：《电子科技大学》2016年博士论文

【摘要】：非制冷红外探测器已广泛地应用于军事、边防、消防、工业检测、交通等各个领域,人们对于探测器的性能要求也越来越高;为满足此要求,开展高性能探测器芯片研究应运而生。高性能意味着具有更高信噪比、更高效率,非理想效应的自适应补偿功能;同时还应满足大阵列、轻质量等需求。本论文以完成高性能非制冷红外探测器芯片一体化设计为目标,研究了一体化设计高性能系统芯片所需的主要关键技术。所涉及到的关键技术包括:探测器像元建模技术、探测器温度补偿技术、探测器芯片片上ADC技术、探测器芯片非均匀性校正技术、探测器芯片数字控制技术。论文的主要研究内容综述如下:1、研究了微测辐射热计型探测器像元电学设计平台兼容的一体化设计模型。通过数学推导和参数仿真,提出了涵盖器件光-热-电多物理场特性的线性模型,其可供电学设计平台使用,以辅助探测器系统一体化设计。该模型与经典模型在探测器温度变化40K时偏差小于5%,具有良好的精度。2、研究了探测器的温度补偿技术,包含自热效应补偿和衬底温度补偿。针对自热效应提出使用片上电流DAC或片上电阻DAC的方式进行补偿。针对衬底温度导致的非理想效应提出引入补偿盲像元的方案用于补偿衬底温度的影响。对于电压偏置型红外读出电路,以采样运放跨阻的形式引入补偿盲像元;对于电流偏置型红外读出电路,以积分器积分电阻的形式的引入补偿盲像元。利用像元一体化设计模型仿真优化设计。经样片测试后在温度变化为80K时,采用所提温度补偿技术的探测器的输出变化率约为20%,其响应率变化率约为40%。3、研究了探测器的片上ADC,包括芯片级ADC和列级ADC。首先由使用像元一体化设计模型的读出电路仿真结果提出片上ADC的性能需求,然后分别研究芯片级ADC和列级ADC。在芯片级ADC方面,以Pipeline ADC为代表展开研究。首先基于Matlab设计并开发了一套Pipeline ADC功耗优化结构软件,并由该软件确定了两种低功耗Pipeline ADC结构。然后提出了一种基于扰动注入(Dither)和动态元件匹配(Dynamic Element Match,DEM)的数字后台算法,以及一种准实时校准的数字前台校准方案,该方案可同时实现连续性校准和增益校准,并将它们分别应用到所提低功耗结构中。由实物样品测试知,使用数字后台算法的Pipeline ADC功耗为299.93mW,DNL为+0.84LSB/-0.94LSB,INL为+0.99LSB/-1.19LSB;而使用数字前台算法的Pipeline ADC功耗为280.96mW,DNL为+0.86LSB/-0.75LSB,INL为+1.53LSB/-1.41LSB。在列级ADC方面,以Single Slope ADC为代表展开研究。为了提高Single Slope ADC的转换速率,本文提出了半周期计数法、两步比较法以及行划分法三种方案;为加强Single Slope ADC信号在探测器芯片上远距离传输时的准确性,提出了电流传输方案,避免信号误码。通过将补偿盲像元引入ADC参考电压的产生电路,获得了具有温度补偿功能的Single Slope ADC,该结构可称为数字温度补偿结构。通过样品测试,单个该Single Slope ADC实际21.86mW,估算其应用于1280×1024阵列时的总功耗为290.19mW,DNL为+0.72LSB/-0.71LSB,INL为+1.18LSB/-1.09LSB。当衬底温度变化80K时,输出数字码658个数字码,占数字动态范围的16.1%,响应率变化率为40.6%。4、研究了探测器的非均匀校正方案,针对本论文重点研究的三种读出电路结构分别提出了非均匀性校正方案以及流程。对于电压偏置结构、电流偏置结构,本论文提出以片上电压DAC调节它们的跨阻运放参考电压,从而实现一点温度补偿。针对该方法设计了一种精度和范围可调的片上电压DAC,该DAC具有4种电压调节范围。由样片测试,电压偏置结构的FNP可降低为11.8mV,电流偏置结构的FNP被降低到10.4mV。对于数字温度补偿结构,本论文提出使用两个片上电流DAC调节其偏置电流,从而实现两点温度补偿。由样片测试,温度补偿ADC结构的FNP为127.3mV。5、在数字控制技术方面,研究了阵列扫描方式、帧信号和逐点校正信号的输入方案以及读出结果的输出方案。将电压偏置结构+Single Slope ADC的ROIC在640×512的阵列下设计制作了大阵列探测器芯片,性能测试结果为平均响应率为8.83codes/K,约为7.33mV/K;RMS噪声为325.3μV,FPN噪声为12.1mV,NETD为62.33mK。
[Abstract]:Uncooled infrared detectors have been widely used in various fields such as military, border defense, fire protection, industrial detection and transportation, and the performance requirements of detectors are becoming higher and higher. In order to meet this requirement, high performance detector chip research has been developed. High performance means that it has higher signal-to-noise ratio, more efficient and non ideal effect. In order to complete the design of high performance uncooled infrared detector chip integrated design, the main key technologies needed for integrated design of high performance system chip are studied in this paper. The key technologies involved include: detector pixel modeling technology, detector temperature supplement The compensation technology, the ADC technology on the chip chip, the non uniformity correction technology of the detector chip and the digital control technology of the detector chip are summarized as follows: 1, the integrated design model of the compatible design platform of the micrometer radiation thermeter type detector is studied. The culvert is put forward by mathematical deduction and parameter simulation. A linear model of the characteristics of the multi physical field of light and thermal electric field, which can be used to assist the integrated design of the detector system. The model and the classic model have a deviation of less than 5% and a good precision.2 when the temperature change of the detector is 40K. The temperature compensation technique of the detector is studied, including the self thermal effect compensation and the substrate temperature. To compensate for the self heat effect, the use of the on-chip current DAC or the on-chip resistance DAC is proposed. The compensation blind pixel scheme is introduced to compensate the influence of the substrate temperature for the non ideal effect caused by the substrate temperature. For the current biased infrared readout circuit, the compensation blind pixel is introduced in the form of integrator integral resistance. The design model of the pixel integration is used to simulate the optimization design. When the temperature change is 80K, the output change rate of the detector using the proposed temperature compensation technique is about 20%, and the response rate is about 40%.3. The on-chip ADC of the detector, including chip level ADC and column level ADC., is first proposed by the read-out circuit simulation results using the pixel integrated design model, and then the chip level ADC and the column level ADC. are studied respectively in the chip level ADC, and Pipeline ADC is considered as the representative. First, the design and development of the Pipeline ADC are designed and developed on Matlab. A set of Pipeline ADC power optimization structure software is used to determine two kinds of low power Pipeline ADC structures. Then a digital background algorithm based on disturbance injection (Dither) and dynamic component matching (Dynamic Element Match, DEM) is proposed, and a quasi real-time calibration scheme of digital front desk is proposed. The scheme can be implemented simultaneously. Continuous calibration and gain calibration are applied to the proposed low power structure. The Pipeline ADC power consumption of the digital background algorithm is 299.93mW, the DNL is +0.84LSB/-0.94LSB, and the INL is +0.99LSB/-1.19LSB, while the Pipeline ADC power consumption of the digital front algorithm is 280.96mW and DNL is +0.86LSB/-0.75LSB. In order to improve the conversion rate of Single Slope ADC, L is the representative of +1.53LSB/-1.41LSB. in the column level ADC. In order to improve the conversion rate of Single Slope ADC, this paper proposes a semi periodic counting method, two step comparison method and three schemes of line division, and the accuracy of enhancing the long distance transmission of Single Slope ADC signal on the probe chip. The current transmission scheme avoids the signal error code. By introducing the compensation blind pixel into the ADC reference voltage generating circuit, the Single Slope ADC with the temperature compensation function is obtained. The structure can be called the digital temperature compensation structure. The total work of the 1280 * 1024 array is estimated by the sample test and the actual 21.86mW of the single Single Slope ADC. The consumption is 290.19mW, DNL is +0.72LSB/-0.71LSB, INL is +1.18LSB/-1.09LSB. when the substrate temperature changes 80K, the output digital code is 658 digital codes, which accounts for 16.1% of the digital dynamic range and the response rate change rate is 40.6%.4. The non uniform correction scheme of the detector is studied. The non uniformity of the three readout circuit structures which are mainly studied in this paper are put forward respectively. The uniformity correction scheme and process. For voltage bias structure and current bias structure, this paper proposes to adjust their cross resistance amplifier reference voltage by DAC on chip voltage to achieve a point of temperature compensation. In this method, a precision and range adjustable voltage DAC is designed for this method. The DAC has 4 range of voltage regulation. The voltage bias structure of the FNP can be reduced to 11.8mV, the FNP of the current bias structure is reduced to the 10.4mV. for digital temperature compensation structure. This paper proposes to use two on-chip current DAC to adjust its bias current to achieve two point temperature compensation. The input scheme of the array scanning, the frame signal and the point by point correction signal and the output scheme of the readout result are studied. A large array detector chip is designed and produced by the voltage biased structure of +Single Slope ADC under 640 x 512 array. The performance test result is that the average response rate is 8.83codes/K, about 7.33mV/K, and the RMS noise is 325.3. V, FPN noise is 12.1mV, NETD is 62.33mK.
【学位授予单位】：电子科技大学
【学位级别】：博士
【学位授予年份】：2016
【分类号】：TN215

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