基于非二进制量化算法的逐次逼近模数转换器的设计

发布时间：2018-06-22 04:23

本文选题：模数转换器 + 逐次逼近ADC　；参考：《电子科技大学》2016年博士论文

【摘要】：作为连接外部世界模拟信号和系统内部数字信号的桥梁,模拟数字转换器(ADC)广泛应用于数字多媒体、通信、生物医疗以及传感控制等领域,其速度、精度以及功耗等性能指标直接影响着整机系统的处理能力。随着工艺尺寸的不断缩小以及电源电压的不断降低,模拟电路设计面临巨大挑战。但逐次逼近模数转换器(SAR ADC)仅含一个模拟模块,其整体结构简单且功耗面积小,因此在小尺寸工艺下易于实现,较其他ADC结构优势凸显。然而,由于其串行的工作模式,SAR ADC的速度较低,造成其应用受限。另一方面,随着ADC分辨率增大,对DAC电容的匹配精度要求提高,导致电容值急剧增大。这使得SAR ADC在高精度应用中受到功耗和速度的双重限制。针对这些问题,本文进行了深入的研究和讨论,包括非二进制编码原理、适用于非二进制量化的DAC结构、非二进制DAC的速度优化设计方案、电容失配的校正技术、异步时序电路的设计以及自校正带隙基准电路的设计等,主要的研究工作和创新如下:1.采用非二进制量化算法的SAR ADC系统架构研究:本文首先对传统的二进制SAR ADC的转换速度进行了理论分析。由于量化每一位时DAC的建立精度都需要达到0.5 LSB,导致DAC所需的建立时间较长,限制了ADC整体的采样速率。为此,本文对非二进制量化算法进行了研究。通过将数字编码的基数设为小于2的分数,可以在量化过程中引入冗余量,使得同一个输入信号可以被两个不同的非二进制编码量化,从而放宽对DAC建立精度的要求。然后,针对分数权重量化算法在实际设计中存在匹配差、编码转换时存在截断误差、无法利用分段电容阵列等问题,提出了基于整数权重的量化算法。在此基础上,又提出了两种适用于非二进制量化的DAC结构,即基于共模电压复位的DAC和电容分裂式DAC。通过将DAC产生的参考电压置于冗余范围的中间,将DAC的建立精度从0.5 LSB扩大到冗余量的一半。最后,提出了一种对DAC电容进行优化设计的方案,以最大限度地利用冗余量的优势来提高整体的转换速度。2.SAR ADC电容失配的校正技术研究:为了利用小电容实现高精度的SAR ADC,需要对电容失配进行校正。本文提出了三种不同的校正技术,包括模拟域前台校正、模拟域后台校正以及数字域后台校正。其中两种模拟域校正适用于二进制SAR ADC,其基本思想均是将待校正电容与其所有的低位电容之和进行比较,然后对二者之差进行补偿。针对非二进制SAR ADC,本文提出了一种基于电容互换的数字域后台校正。DAC中的终端电容被视为参考电容,每个输入信号被量化两次,在第二次量化时待校正的单位电容与参考电容交换位置。根据两次量化结果之差,利用LMS算法对待校正的单位电容的数字权重进行更新。为了减少所需校正的电容的个数,本文还提出了带双参考电容的校正算法。3.自校正带隙基准的设计与实现:带隙基准为ADC提供了一个不随温度和电源电压变化的参考电压,但传统带隙基准的初始精度不高。为此,本文提出了一种自校正的带隙基准电路。电路上电后,通过交换需要匹配的器件的相对位置,可以得到两个大小不同的初始基准电压。然后通过自动修调,使电路最终输出的基准电压等于两个初始基准电压的平均值。该设计达到了和斩波技术相同的效果,但避免了时钟信号的持续作用,消除了电压的抖动,同时也避免了传统修调技术中需要对各颗芯片单独进行人工修调的弊端,提高了系统的智能化程度。该电路在65 nm CMOS工艺上进行了流片验证。测试结果显示,电路工作正常,校正后基准电压的3σ误差率从±12.6%减小到±1.0%,温度系数为23.6 ppm/°C,PSRR达到62.8 dB。4.基于非二进制量化算法的SAR ADC的设计与实现:本文设计了一个12位5 MSPS的非二进制SAR ADC。为了进一步提高速度,本文采用了带Self-Timed控制模式的异步时序,并采用了一种自适应延迟电路,使得异步时序中各位的量化时间可以根据实际的采样率进行调整。DAC选用了基于共模电压复位的结构,基于整数权重来进行设计,并采用了分段电容阵列来降低总电容和面积。用自举开关对输入信号进行采样以提高采样线性度。比较器采用了两级预放大加锁存的结构以降低噪声。进行校正的数字电路通过Verilog代码综合后自动生成,并与模拟电路部分集成在一颗芯片上。该ADC在65 nm CMOS工艺上进行了流片验证,核心电路面积为0.77 mm×0.65 mm。测试结果显示,电路工作正常,校正后各项性能指标均有明显改善,DNL和INL分别为0.73 LSB和1.24 LSB,SNDR和SFDR分别达到67.7 dB和85.5 dB,ENOB为11.0位,功耗约为6.87 mW。
[Abstract]:As a bridge to connect the analog signals of the external world and the internal digital signals in the system, analog digital converter (ADC) is widely used in the fields of digital multimedia, communication, biological medical and sensing control. Its speed, precision and power consumption have a direct impact on the processing capability of the whole system. The analog circuit design faces great challenges. But the successive approximation analog to analog digital converter (SAR ADC) contains only one analog module, its overall structure is simple and the power consumption is small, so it is easy to realize under the small size process and the advantages of other ADC structures are prominent. However, because of its serial working mode, the speed of SAR ADC The lower application is limited. On the other hand, as the resolution of ADC increases, the matching precision of the DAC capacitance is increased and the capacitance value increases sharply. This makes the SAR ADC be restricted by the dual power and speed in high precision applications. It is suitable for non binary quantization DAC structure, non binary DAC speed optimization design scheme, capacitor mismatch correction technique, asynchronous sequential circuit design and self-tuning bandgap reference circuit design. The main research work and innovation are as follows: 1. research on SAR ADC system architecture using non binary quantization algorithm: first of all, The conversion speed of the traditional binary SAR ADC is theoretically analyzed. As the accuracy of each DAC is quantified, the establishment precision of DAC needs to reach 0.5 LSB, which leads to the longer time required for DAC to limit the sampling rate of the ADC as a whole. The fraction can be introduced in the quantization process, so that the same input signal can be quantized by two different non binary codes. Thus, the requirement for the accuracy of DAC is relaxed. Then, there is a matching difference in the actual design for the fractional weighting algorithm, and there is a truncation error in the coding conversion, and the piecewise capacitance matrix can not be used. A quantization algorithm based on integer weights is proposed. On this basis, two kinds of DAC structures for non binary quantization are proposed, that is, the DAC based on the common mode voltage reset and the capacitive DAC. are placed in the middle of the redundant range by the reference voltage produced by the DAC, and the accuracy of the establishment of DAC is expanded from 0.5 LSB to redundancy. In the end, a scheme to optimize the design of DAC capacitors is proposed in order to maximize the advantage of redundancy to improve the overall conversion rate of.2.SAR ADC capacitor mismatch. In order to use small capacitors to achieve high precision SAR ADC, it is necessary to correct the mismatch of capacitance. This paper presents three different kinds of corrections. Positive technology, including analog domain front end correction, analog domain background correction and digital domain background correction, two analog domain corrections are applicable to binary SAR ADC. The basic idea is to compare the sum of the uncorrected capacitance to the sum of all low level capacitors, and then compensate the difference of the two. For non binary SAR ADC, this paper proposes The terminal capacitance in a digital domain backstage correction.DAC based on capacitance interchangeability is considered as a reference capacitor, each input signal is quantized two times and the unit capacitance to be corrected at the second time of quantization is exchanged with the reference capacitance. According to the difference between the two quantization results, the LMS algorithm is used to deal with the digital weight of the corrected unit capacitance. In order to reduce the number of capacitors required to be corrected, this paper also proposes the design and implementation of a self-tuning bandgap reference.3. with a double reference capacitance correction algorithm. The band gap reference provides a reference voltage without changing the temperature and the power supply voltage for the ADC, but the original precision of the traditional band gap reference is not high. A corrected bandgap reference circuit. After the circuit is on the circuit, two initial reference voltages of different sizes can be obtained by exchanging the relative position of the matched device. Then the voltage of the final output of the circuit is equal to the average of the two initial reference voltages by automatic tuning. The design achieves the same effect as the chopper technique. However, it avoids the continuous function of the clock signal and eliminates the jitter of the voltage. At the same time, it avoids the defects of the traditional trimming technology which needs to repair each chip separately, and improves the intelligentized degree of the system. The circuit has carried out the flow sheet verification in the 65 nm CMOS process. The test results show that the circuit works well and the calibrated datum. The 3 Sigma error rate of voltage is reduced from 12.6% to 1%, temperature coefficient is 23.6 ppm/ C, and PSRR reaches 62.8 dB.4. based on the design and implementation of SAR ADC based on non binary quantization algorithm. In this paper, a non binary SAR ADC. of 12 bit 5 MSPS is designed to further improve the speed. This paper uses the asynchronous sequence with Self-Timed control mode, and takes the asynchronous sequence with the Self-Timed control mode. Using an adaptive delay circuit, the quantization time in asynchronous sequence can be adjusted according to the actual sampling rate..DAC is based on the common mode voltage reset structure, based on the integer weight weight, and the sectional capacitance array is used to reduce the total capacitance and area. The input signal is sampled by the bootstrap switch. In order to improve the sampling linearity. The comparator uses a two stage preamplifier and latched structure to reduce the noise. The digital circuit is automatically generated by the Verilog code, and is integrated with the analog circuit on a chip. The ADC performs a flow sheet verification on the 65 nm CMOS process, with a core circuit area of 0.77 mm * 0.65 mm. The test results show that the circuit works well and the performance indexes are improved obviously. DNL and INL are 0.73 LSB and 1.24 LSB respectively. SNDR and SFDR are 67.7 dB and 85.5 dB respectively, ENOB is 11, and power consumption is 6.87 mW..
【学位授予单位】：电子科技大学
【学位级别】：博士
【学位授予年份】：2016
【分类号】：TN792

【相似文献】