面向心电信号检测的低功耗处理器体系结构研究
发布时间：2018-09-08 18:32
【摘要】：基于无线节点的心电信号检测正在得到越来越广泛的应用,为了保证检测设备的便携性和易用性,需要设计一款低功耗运行的心电信号处理器,以延长设备的续航时间,提升设备的使用舒适性。本文基于现有商用处理器体系结构,面向心电信号检测的便携应用需求,针对处理器的低功耗设计方法开展深入研究。通过引入块指令方法,改变处理器的指令运行方式,在不损失处理器灵活性的前提下,在体系结构层面降低处理器功耗,提升心电信号检测设备的续航。主要内容如下：分析典型心电应用程序,针对测试数据标签不平衡的现象,引入迁移算法改进现有学习算法,提升信号判断的准确率。引入块指令方法优化功耗。通过分析心电应用汇编指令级特征：指令聚类多、内存访问集中、核心算法固定、程序流分支少,通过聚合原子操作形成块指令,改变处理器基于原子指令运行的方式,减少处理器取指、译码和运行时的功耗。提出基于块指令的编译运行框架。使用块指令调度模块聚合原子指令优化形成块指令；引入字典压缩、寄存器重分配、预先译码、同类操作合并等利于硬件低功耗执行的技术,在压缩指令空间的同时,降低处理器运行功耗。提出基于块指令执行的处理器架构。改进现有商业处理器架构,以块为最基本的操作单元完成指令的执行,化零为整,优化指令操作。引入主动内存,内存主动提供待执行的指令,驱动处理器完成指令执行。主动内存的引入增强了内存的灵活性,减少了总线的传输,降低了处理器的设计难度,去除了处理器的取指、译码逻辑。引入自驱动低功耗运算单元。运算单元自我驱动,主动搜索能够执行的指令,简化处理器发射逻辑,提升处理器运行效率。算术运算单元操作数长度自适应,多路数据并行运算,减少处理器运行时间。引入低功耗内存访问单元。使用存储载入操作的历史轨迹预判即将访问的内存地址,基于热点行自搜索,追踪热点程序,预先载入高速缓存状态,去除冗余的内存访问和比较操作。该单元还能根据历史信息,判定载入的数据是否为常数,缓存常数,减少内存访问。本文提出的块指令方法,对于降低处理器功耗具有积极的作用。实验表明,针对心电应用,基于块指令的低功耗处理器相对于传统处理器可以降低35%-40%左右的功耗。
[Abstract]:ECG detection based on wireless nodes is becoming more and more widely used. In order to ensure the portability and ease of use of the detection equipment, a low power consumption ECG processor is needed to prolong the device's life. Enhance the comfort of the use of equipment. Based on the existing commercial processor architecture and the portable application requirements of ECG signal detection, the low power design method of the processor is deeply studied in this paper. By introducing the block instruction method, the instruction operation mode of the processor is changed, and the processor power consumption is reduced at the architecture level without losing the flexibility of the processor, and the continuance of the ECG detection device is improved. The main contents are as follows: analyze the typical ECG application program and introduce the migration algorithm to improve the existing learning algorithm to improve the accuracy of signal judgment. Block instruction method is introduced to optimize power consumption. By analyzing the characteristics of assembly instruction level in ECG application, such as more instruction clustering, memory access set, fixed core algorithm, less branch of program flow, block instruction formed by aggregation atomic operation, the operation mode of processor based on atomic instruction is changed. Reduce the power consumption of processor fetch, decode, and run time. In this paper, a block instruction based framework for compiling and running is proposed. Using block instruction scheduling module to aggregate atomic instruction optimizes to form block instruction, introducing dictionary compression, register redistribution, pre-decoding, similar operation merging and other techniques which are conducive to low power execution of hardware, while compressing instruction space. Reduce processor running power consumption. A processor architecture based on block instruction execution is proposed. The existing commercial processor architecture is improved to complete instruction execution with block as the most basic operation unit and to optimize instruction operation. Active memory is introduced. Memory actively provides instructions to be executed, driving the processor to complete instruction execution. The introduction of active memory enhances the flexibility of memory, reduces the transmission of bus, reduces the difficulty of processor design, and removes the logic of the processor. Self-driven low power computing unit is introduced. The operation unit is self-driven, actively searches for the instructions that can be executed, simplifies the processor's transmit logic, and improves the processor's running efficiency. The arithmetic operation unit adapts to the Operand length and the multiplex data parallel operation reduces the processor running time. A low power memory access unit is introduced. The memory address to be accessed is predicted by using the historical track of the storage loading operation, based on the hot spot line self-search, tracking the hot spot program, pre-loading the cache state, removing redundant memory access and comparing operations. The unit can also determine whether the loaded data is constant, cache constant and reduce memory access according to historical information. The block instruction method proposed in this paper plays an active role in reducing processor power consumption. Experiments show that the low power processor based on block instruction can reduce the power consumption by 35% to 40% compared with the traditional processor for ECG applications.
【学位授予单位】：浙江大学
【学位级别】：博士
【学位授予年份】：2016
【分类号】：R540.4;TN911.23
本文编号：2231346
[Abstract]:ECG detection based on wireless nodes is becoming more and more widely used. In order to ensure the portability and ease of use of the detection equipment, a low power consumption ECG processor is needed to prolong the device's life. Enhance the comfort of the use of equipment. Based on the existing commercial processor architecture and the portable application requirements of ECG signal detection, the low power design method of the processor is deeply studied in this paper. By introducing the block instruction method, the instruction operation mode of the processor is changed, and the processor power consumption is reduced at the architecture level without losing the flexibility of the processor, and the continuance of the ECG detection device is improved. The main contents are as follows: analyze the typical ECG application program and introduce the migration algorithm to improve the existing learning algorithm to improve the accuracy of signal judgment. Block instruction method is introduced to optimize power consumption. By analyzing the characteristics of assembly instruction level in ECG application, such as more instruction clustering, memory access set, fixed core algorithm, less branch of program flow, block instruction formed by aggregation atomic operation, the operation mode of processor based on atomic instruction is changed. Reduce the power consumption of processor fetch, decode, and run time. In this paper, a block instruction based framework for compiling and running is proposed. Using block instruction scheduling module to aggregate atomic instruction optimizes to form block instruction, introducing dictionary compression, register redistribution, pre-decoding, similar operation merging and other techniques which are conducive to low power execution of hardware, while compressing instruction space. Reduce processor running power consumption. A processor architecture based on block instruction execution is proposed. The existing commercial processor architecture is improved to complete instruction execution with block as the most basic operation unit and to optimize instruction operation. Active memory is introduced. Memory actively provides instructions to be executed, driving the processor to complete instruction execution. The introduction of active memory enhances the flexibility of memory, reduces the transmission of bus, reduces the difficulty of processor design, and removes the logic of the processor. Self-driven low power computing unit is introduced. The operation unit is self-driven, actively searches for the instructions that can be executed, simplifies the processor's transmit logic, and improves the processor's running efficiency. The arithmetic operation unit adapts to the Operand length and the multiplex data parallel operation reduces the processor running time. A low power memory access unit is introduced. The memory address to be accessed is predicted by using the historical track of the storage loading operation, based on the hot spot line self-search, tracking the hot spot program, pre-loading the cache state, removing redundant memory access and comparing operations. The unit can also determine whether the loaded data is constant, cache constant and reduce memory access according to historical information. The block instruction method proposed in this paper plays an active role in reducing processor power consumption. Experiments show that the low power processor based on block instruction can reduce the power consumption by 35% to 40% compared with the traditional processor for ECG applications.
【学位授予单位】：浙江大学
【学位级别】：博士
【学位授予年份】：2016
【分类号】：R540.4;TN911.23
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