纳米级SRAM单粒子翻转效应及其诱导的软错误研究

发布时间：2018-10-05 17:50

【摘要】：近年来随着我国航天科技不断攀升,对辐照环境应用微处理器的高可靠性需求越发迫切。SRAM作为微处理器核心存储部件占用较大芯片面积,并且对辐照引发的单粒子翻转效应(SEU)极为敏感。SEU诱导SRAM产生软错误后,能够导致微处理器不能正常工作,因此开展SRAM的SEU和软错误研究十分必要。工艺尺寸进入纳米级后,集成电路器件间的电荷共享愈发严重,使得纳米级SRAM单元的SEU敏感性发生改变,导致已有多种加固方法失效。同时,小尺寸SRAM单元中也产生了新的单粒子翻转恢复效应(SEUR),通过增强SEUR可降低SRAM的SEU敏感性。基于三维堆叠技术的3D SRAM把传统SRAM在垂直方向上进行堆叠,并使用TSV进行垂直互联,解决了传统SRAM遇到的诸多瓶颈,但处于辐照环境中的3D SRAM依然会受到SEU危害而产生软错误。3D SRAM堆叠结构使SEU产生和传播更加复杂,进而增加了3D SRAM软错误分析的难度。同时,三维堆叠技术使用的TSV会与入射单粒子发生碰撞,进而对3D SRAM软错误特性产生影响。针对纳米级SRAM单元和3D SRAM中SEU和软错误的新特性,本文开展了相关研究并取得了以下几个方面的研究成果:(1)利用3D TCAD全器件模拟,研究电荷共享对纳米级SRAM单元SEU敏感特性的影响。根据40nm商用SRAM单元版图,对单元内所有晶体管均建立3D TCAD器件模型。然后分别在有/无电连接关系和不同LET条件下模拟得到SEU敏感面积。模拟结果表明电荷共享可使PMOS的SEU敏感面积减小37.5%,使NMOS的SEU敏感面积减小65.1%。通过深入分析不同条件下SEU敏感面积的差别,发现基于电荷共享的SEUR可以减小PMOS的SEU敏感性,而开态PMOS通过帮助吸收沉积电荷并产生补偿电流来减小NMOS的SEU敏感面积。此外,研究还表明SRAM单元中NMOS比PMOS更加敏感。(2)分别深入研究SRAM单元内关态PMOS和开态PMOS之间,以及关态PMOS和开态NMOS之间的SEUR效应,并讨论增强SEUR的方法。基于TCAD器件/电路混合模拟,发现关态PMOS和开态PMOS间SEUR的产生不仅依赖于电荷共享,并且还需要从级器件的电荷收集强于主级器件的电荷收集。提出了DSD和DPI两种版图布局来增强两PMOS间的SEUR。垂直入射模拟中同传统版图相比,DSD和DPI版图可以分别减少4.26%和31.56%的SEU敏感面积。在斜入射模拟中只有DPI版图可极大增加SEUR的产生概率。本文还研究了由关态PMOS的电荷收集和开态NMOS的延迟电荷收集触发的新型SEUR。此SEUR受PMOS影响较小而受NMOS影响较大,减少同反相器中PMOS和NMOS间距可以增强这种SEUR,并且其诱导SET的宽度饱和值等于SEU产生时间与SRAM单元反馈延迟之和。(3)利用基于蒙特卡洛方法的SRIM和Geant4工具研究3D SRAM堆叠结构对软错误特性的影响。利用SRIM工具分析重离子在三维堆叠结构中的射程,模拟结果表明重离子能量大于22MeV/u后即可穿过6层管芯堆叠的模型,由此可知3D SRAM中每层都可能会产生软错误。利用Geant4模拟得到复杂三维堆叠结构模型中各层管芯敏感层中的沉积电荷量,分析发现在低能重离子轰击条件下,各层管芯的软错误特性有较大不同,但在高能重离子轰击条件下,这种差别会消失,并且底层管芯更容易发生较为严重的MCU。研究中还发现TSV对入射重离子具有阻碍作用,并且TSV可以降低周围敏感单元的翻转截面。(4)搭建3D SRAM软错误分析平台,分析3D SRAM的软错误特性。利用业界公认的SET、SEU模拟方法和成熟工具,建立3D SRAM软错误分析平台,此平台可快速、准确分析和评估3D SRAM的软错误。基于此平台对同规模的2D SRAM、字线划分3D SRAM和位线划分3D SRAM分别进行了软错误分析。分析结果表明:垂直轰击静态测试中三种SRAM的翻转截面几乎相同,但随机入射角模拟中3D SRAM翻转截面要大于2D SRAM;静态测试中字线划分3D SRAM会产生更加严重的MBU,因此位线划分3D SRAM更加适合应用于辐照环境;动态测试中三种SRAM的组合逻辑电路被轰击后都会引发严重的MBU;由于TSV周围敏感单元数量较少,TSV只能降低3%左右的翻转截面。
[Abstract]:With the increasing of space science and technology in our country in recent years, the high-reliability demand for application of microprocessor to radiation environment becomes more and more urgent. SRAM, as a core storage component of the microprocessor, occupies a larger chip area and is extremely sensitive to the single particle inversion effect (SEU) initiated by irradiation. It is necessary to carry out SEU and soft error research of SRAM after the SEU induced soft error in SRAM. after the process size enters the nanometer level, the charge sharing between the integrated circuit devices becomes more serious, so that the SEU sensitivity of the nano-scale SRAM cells is changed, and a plurality of reinforcing methods are caused to fail. At the same time, a new single particle inversion recovery effect (SEUR) is also generated in small size SRAM cells, which can reduce the SEU sensitivity of SRAM by enhancing SEUR. The 3D SRAM based on the three-dimensional stacking technology stacks the traditional SRAM in the vertical direction, and the vertical interconnection is performed using the TSVs, so that a plurality of bottlenecks encountered by the conventional SRAM are solved, However, the 3D SRAM in the irradiation environment will still suffer from the SEU hazard. The 3D SRAM stack structure makes SEU generate and propagate more complex, and then increases the difficulty of soft error analysis of 3D SRAM. meanwhile, the TSV used by the three-dimensional stacking technology can collide with the incident single particle, and further influence the soft error characteristics of the 3D SRAM. In view of the new features of SEU and soft error in nanoscale SRAM cells and 3D SRAM, the relevant research has been carried out and the following achievements have been obtained: (1) The effect of charge sharing on the SEU sensitive characteristics of nanoscale SRAM cells is studied by using 3D TCAD system-wide simulation. Based on the 40nm commercial SRAM cell layout, 3D TCAD device model was built for all transistors in the cell. The SEU sensitive area is then simulated under/ without electrical connection and under different LET conditions, respectively. The simulation results show that charge sharing can reduce the SEU sensitive area of PMOS by 37. 5%, and reduce the SEU sensitive area of NMOS by 65.1%. By analyzing the difference of SEU sensitive area under different conditions, it is found that SEUR based on charge sharing can reduce the SEU sensitivity of PMOS, while on-state PMOS reduces the SEU sensitive area of NMOS by helping to absorb the deposited charge and generate compensation current. In addition, the study shows that NMOS is more sensitive to NMOS than PMOS in SRAM cells. (2) the SEUR effect between the off-state PMOS and the ON-state PMOS and the OFF-state PMOS and the ON-state NMOS are researched in the SRAM cell respectively, and the method for enhancing SEUR is also discussed. Based on the TCAD device/ circuit hybrid simulation, it is found that the generation of SEUR between the off-state PMOS and the ON-state PMOS depends not only on charge sharing, but also the charge collection from the stage device is stronger than that of the main-stage device. Two layouts of DSD and DPI are proposed to enhance the SEUR between two PMOS transistors. Compared with the traditional layout in the vertical incident simulation, the DSD and DPI layout can reduce the SEU sensitive area of 4.26% and 31. 56%, respectively. Only DPI layout can greatly increase the generation probability of SEUR in oblique incidence simulation. This paper also studies the new SEUR of delayed charge collection triggered by charge-collection and open-state NMOS of off-state PMOS. This SEUR is affected by the PMOS and is greatly influenced by the NMOS, so that the SEUR can be enhanced by reducing the PMOS and NMOS spacing in the same inverter, and the width saturation value of the induced SET is equal to the sum of the SEU generation time and the SRAM cell feedback delay. (3) Using the SRIM and Geant4 tools based on Monte Carlo method to study the effect of 3D SRAM stack structure on soft error characteristics. Using the SRIM tool to analyze the range of heavy ions in the three-dimensional stacked structure, the simulation results show that the heavy ion energy can pass through the model of the six-layer die stack after the heavy ion energy is greater than 22MeV/ u, thus it can be seen that each layer in the 3D SRAM may produce soft errors. By using Geant4 simulation to obtain the deposition charge in the sensitive layers of each layer die in the complex three-dimensional stacked structure model, the analysis shows that under the condition of low energy heavy ion bombardment, the soft error characteristics of each layer die are greatly different, but under the condition of high energy heavy ion bombardment, the difference can disappear, and the underlying die is more susceptible to a more severe mcu. It is also found that TSVs have a blocking effect on incident heavy ions, and TSV can reduce the inverted cross section of the surrounding sensitive cells. and (4) constructing a 3D SRAM soft error analysis platform, and analyzing the soft error characteristics of the 3D SRAM. Based on the established SET, SEU simulation method and mature tool, the 3D SRAM soft error analysis platform is established, which can quickly and accurately analyze and evaluate the soft error of 3D SRAM. Based on this platform, soft error analysis of 2D SRAM, word line division 3D SRAM and bit line division 3D SRAM were carried out. The results show that the flip section of the three SRAM is almost the same in the vertical bombardment static test, but the inverted cross section of the 3D SRAM is larger than 2D SRAM in the random incident angle simulation; the word line division 3D SRAM in the static test will produce more serious MBU, Therefore, the bit line division 3D SRAM is more suitable for application in the irradiation environment; the combinational logic circuits of the three SRAM in the dynamic test cause serious MBU; due to the small number of sensitive units around the TSV, the TSV can only reduce the inverted cross section of about 3%.
【学位授予单位】：国防科学技术大学
【学位级别】：博士
【学位授予年份】：2016
【分类号】：TP333

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