超高频RFID读写器中LNA的研究与设计

发布时间：2018-04-20 05:11

本文选题：LNA + 射频识别　；参考：《华南理工大学》2015年硕士论文

【摘要】：射频识别技术是一种非接触式自动识别无线通信技术,它有防磁、耐高温、读写距离大等优势。广泛应用于门禁系统、身份识别、非接触式付费卡、车辆防盗系统、物流系统等多个领域中应用射频识别技术主要有四种类型,其中860~960MHz的超高频射频识别系统能重复读取多个标签、且数据容量大,是未来的发展趋势。低噪声放大器(LNA)是射频识别读写器的第一级,直接影响整个接收机的性能。随着射频识别技术的深入推广和使用、集成工艺的提高,IC规模越来越大,人们对射频识别系统的要求越来越高,进而对读写器中低噪放的要求也越来越高,在对性能要求越来越高的同时,人们希望系统功耗越来越小,以满足系统续航能力强的实际应用要求,低噪声放大器低功耗电路设计的研究和发展已成为一个研究焦点。针对超高频射频识别读写器应用,本文研究设计其射频前端低噪放电路。针对LNA电路功耗大的问题,本文使MOS管工作在亚阈值区,使其电流小,跨导小,进而系统功耗小。同时为了弥补工作在亚阈值区的MOS管带来的噪声性能变差、增益不足等问题,本文采用电流复用技术和最优噪声匹配方法,最终实现了在较为优良的增益、噪声性能的前提下,降低其功耗的结果。本文采用Global Foundry 180nm CMOS工艺对提出的LNA电路进行了电路设计、版图的设计与物理验证。版图后仿真结果为,本文设计的低噪放电路采用1.8V电源电压,电路功耗为1.8m W,低噪放噪声系数为NF=3.6d B,在中心频率915MHz附近的S参数为,S11=-24.03d B,S22=-19.22d B,输入输出匹配良好。电压增益S21=15.6d B,则电路具有比较高的增益,S12=-46.65d B,可以看出电路有比较好的隔离度。芯片版图面积为630 450(不含pad)。
[Abstract]:Radio frequency identification (RFID) technology is a non-contact automatic identification wireless communication technology. It has the advantages of magnetic resistance, high temperature resistance and long reading and writing distance. RFID technology is widely used in many fields, such as access control system, identity identification, non-contact payment card, vehicle anti-theft system, logistics system, etc. There are mainly four types of RFID technology. The UHF RFID system of 860~960MHz can read multiple tags repeatedly, and the data capacity is large, which is the development trend in the future. LNA (low noise Amplifier) is the first stage of RFID reader, which directly affects the performance of the whole receiver. With the further promotion and application of RFID technology, the scale of integrated technology is increasing, and the requirement of RFID system is becoming higher and higher, and the requirement of low noise amplifier in the reader is becoming higher and higher. At the same time, people hope that the power consumption of the system will become smaller and smaller to meet the practical application requirements of the system with strong endurance. The research and development of low power circuit design of low noise amplifier has become a research focus. Aiming at the application of UHF RFID reader, the RF front end low noise amplifier circuit is studied and designed in this paper. In order to solve the problem of high power consumption in LNA circuits, this paper makes the MOS transistor work in the sub-threshold region, which makes the current and transconductance small, and then the power consumption of the system is low. At the same time, in order to make up for the problem of noise performance and gain deficiency caused by MOS transistor working in sub-threshold region, this paper adopts current multiplexing technology and optimal noise matching method, and finally realizes the premise of better gain and noise performance. The result of reducing power consumption. In this paper, Global Foundry 180nm CMOS process is used to design the proposed LNA circuit, layout design and physical verification. The simulation results are as follows: 1.8V power supply voltage, 1.8 MW power consumption and NF=3.6d B are used in the low noise amplifier circuit. The S parameter near the center frequency 915MHz is S11- 24.03dBU S22 ~ (-19.22) dB, and the input and output match is good. If the voltage gain is S21 ~ (15. 6) dB, the circuit has a higher gain (S _ (12) ~ (-46.65) dB), which shows that the circuit has good isolation. Chip layout area of 630,450 (excluding padger.
【学位授予单位】：华南理工大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TP391.44

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