多转发级别的向量网硬件交换机设计与实现

发布时间：2018-02-26 21:15

本文关键词： 向量网向量地址硬件交换机 NetFPGA 传输面　出处：《北京交通大学》2017年硕士论文　论文类型：学位论文

【摘要】：随着互联网技术的发展和网络用户的大规模增加,现有网络体系在资源控制、QoS、网络安全等方面难以满足网络用户的应用需求,这使得对新型网络体系架构的研究成为人们关注的重要课题。向量网是一种新型网络体系架构,它以向量地址和向量交换为基础,实现了交换节点简单、轻量向量连接、保证QoS、内在可信、向量地址无限可扩展等优势,并通过将控制面和传输面分离开来,减少传输面路由信息收集、更新、维护等工作,提高了数据转发的能力。本论文设计的向量网硬件交换机的主要功能是解析向量地址,转发数据包;支持部分向量网信令,处理少量控制面信息。该硬件交换机的数据处理过程快,资源利用率高。本文根据向量网理论体系,具体做了如下的设计和实现:1.提出一种向量网硬件交换机功能的改进设计方案,实现多级别数据包缓存处理及相关调度算法,多级别数据包解析转发及相关调度算法,使向量交换机可以支持多级别QoS机制;2.在ISE环境,用Verilog语言实现了一种向量网硬件交换机,包括数据包格式的预处理模块,数据转发处理模块,信令支持模块,输出控制模块等,并实验测试了相应功能;3.在NetFPGA开发板上验证了各个模块功能,结果表明可以满足向Xilinx Spartan-3A系统XC3S1400A芯片移植的要求。通过对向量网硬件交换机的设计和实现,并移植于低成本芯片,达到低成本实现1Gbps转发速率的目的,为向量网的进一步部署和应用打下基础。
[Abstract]:With the development of Internet technology and the large-scale increase of network users, the existing network system is difficult to meet the application needs of network users in the aspects of resource control, QoS, network security, etc. This makes the research of new network architecture become an important issue. Vector network is a new network architecture, which is based on vector address and vector switching, and realizes simple switching node and light vector connection. QoS is guaranteed to be inherently credible and vector addresses are infinitely scalable. By separating the control surface from the transmission surface, the routing information collection, updating and maintenance of the transport surface are reduced. The main function of the vector network hardware switch designed in this paper is to resolve the vector address, forward the data packet, support the partial vector network signaling, the main function of this paper is to resolve the vector address, forward the data packet, support the partial vector network signaling, A small amount of control surface information is processed. The data processing process of the hardware switch is fast and the utilization rate of resources is high. In this paper, according to the theory system of vector network, This paper introduces the following design and implementation: 1. An improved design scheme of vector network hardware switch function is proposed, which realizes multi-level packet cache processing and related scheduling algorithm, multi-level packet parsing and forwarding algorithm, and related scheduling algorithm. In the ISE environment, a vector network hardware switch is implemented by using Verilog language, which includes preprocessing module of data packet format, data forwarding processing module, signaling support module, etc. The function of each module is verified on the NetFPGA development board. The result shows that it can meet the requirement of transplanting to the XC3S1400A chip of Xilinx Spartan-3A system. Through the design and implementation of the vector network hardware switch, the output control module and the corresponding function are tested and tested. It is transplanted to low cost chip to achieve the goal of 1Gbps forwarding rate at low cost, which lays the foundation for the further deployment and application of vector network.
【学位授予单位】：北京交通大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TP393.02

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