嵌入式光纤万兆以太网系统设计

发布时间：2018-05-11 21:34

本文选题：万兆以太网 + XAUI接口　；参考：《大连理工大学》2014年硕士论文

【摘要】：视频技术的飞速发展,高分辨率、高帧率图像采集在科学研究和工业生产等领域中发挥着越来越重要的作用,而连续的高分辨率、高帧率图像采集会产生巨大的数据量,因此必须采用具有更高信道容量的通信系统作为传输媒介,才能够实现高速数据图像的可靠传输。基于万兆以太网标准IEEE802.3ae和FPGA技术,设计了传输带宽为lOGbps的嵌入式图像系统。系统由应用层逻辑模块、数据链路层模块和高速串行接口模块三部分组成,其中应用层逻辑模块负责高速传感器的配置和数据收发功能；数据链路层模块负责以太网数据的编解码以及帧校验功能；高速串行接口模块负责将并行数据流转化为高速串行数据流,实现与上位机的通信。硬件设计方面,采用Xilinx公司的型号为Virtex-5LX50T的FPGA作为万兆以太网传输卡的主控芯片,利用FPGA中的IP核实现收发万兆以太网数据协议,利用XAUI核和内置的GTP高速收发器硬核实现高速串行数据的传输；万兆以太网物理层使用Broadcom公司的专用芯片BCM8706,用于实现XAUI接口数据到XFI接口数据的相互转换。BCM8706芯片采用10GBASE-LRM串行传输标准,实现220m的传输距离。光收发器采用Finisar公司的SFP+接口光模块,实现10.3125Gbps光电信号转换和传输。系统软件方面设计主要为FPGA中的逻辑设计和应用程序设计。使用VerilogHDL语言完成FPGA逻辑设计,实现CMOS传感器的配置以及各个模块之间的驱动时序和控制信号；在FPGA中开辟两块双口RAM缓存数据,根据图像传感器的数据传输特点设计了乒乓读写时序,解决海量数据的直传问题。基于开源的编程接口WinPcap和MFC设计了网络数据包获取与恢复应用程序,使用C++语言编程,实现网络数据的直接存储以及图像的回放功能。在论文最后给出系统调试流程及性能分析,经过测试传输卡可以实现10Gbps的数据传输,应用程序可以实现稳定的图像存储与回放功能。
[Abstract]:With the rapid development of video technology, high resolution and high frame rate image acquisition is playing a more and more important role in the fields of scientific research and industrial production, while continuous high resolution and high frame rate image acquisition will produce a huge amount of data. Therefore, the communication system with higher channel capacity must be used as the transmission medium in order to realize the reliable transmission of high-speed data images. Based on the standard IEEE802.3ae and FPGA technology of Gigabit Ethernet, an embedded image system with transmission bandwidth of lOGbps is designed. The system consists of three parts: application layer logic module, data link layer module and high speed serial interface module. The application layer logic module is responsible for the configuration of high speed sensor and the function of data receiving and sending. The data link layer module is responsible for the Ethernet data coding and decoding and the frame checking function, and the high-speed serial interface module is responsible for converting the parallel data stream into the high speed serial data stream to realize the communication with the host computer. In the aspect of hardware design, the FPGA of Virtex-5LX50T of Xilinx Company is used as the main control chip of Gigabit Ethernet transmission card, and the IP core of FPGA is used to realize the data protocol of sending and receiving Gigabit Ethernet. The XAUI core and the hard core of the GTP high-speed transceiver are used to realize the high speed serial data transmission. The physical layer of Gigabit Ethernet uses BCM8706, a special chip of Broadcom Company, to realize the conversion between XAUI interface data and XFI interface data. BCM8706 chip adopts 10GBASE-LRM serial transmission standard and realizes the transmission distance of 220m. The optical transceiver uses Finisar SFP interface optical module to realize 10.3125Gbps photoelectric signal conversion and transmission. The design of system software is mainly logic design and application program design in FPGA. VerilogHDL language is used to complete FPGA logic design, to realize the configuration of CMOS sensor, drive timing and control signal between modules, and to open two blocks of double-port RAM to cache data in FPGA. According to the data transmission characteristics of image sensor, a ping-pong reading and writing time sequence is designed to solve the problem of direct transmission of mass data. The application program of network packet acquisition and recovery is designed based on open source programming interfaces WinPcap and MFC. C language is used to program to realize the direct storage of network data and the function of image playback. At the end of the paper, the system debugging flow and performance analysis are given. After testing the transmission card, the 10Gbps data transmission can be realized, and the application program can realize the stable image storage and playback function.
【学位授予单位】：大连理工大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TP393.11

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