基于FPGA的CAN总线与以太网协议转换卡的实现

发布时间：2018-05-30 20:32

本文选题：CAN总线 + 以太网　；参考：《北京邮电大学》2014年硕士论文

【摘要】：将现场总线技术与以太网技术相结合是当今工业控制领域的热点,现场总线的稳定性实时性与以太网的灵活性都能得到体现。目前应用最广泛的现场总线是CAN总线,CAN总线有成熟的国际标准,被视为最有前途的现场总线之一。本文在Altera公司的FPGA平台上,用RTL设计完成了CAN总线的软核,方便进行功能裁剪和移植,并通过配置Altera公司提供的三速以太网IP核(triple-speed-megacore)来实现以太网的协议,降低开发成本,减少开发周期,最后使用SDRAM转存数据来实现两个协议间的转换。本文一共完成了以下几个方面的工作： 1.完成了CAN协议的RTL设计,包括读写寄存器的设计、位同步设计、位流管理器设计。其中,读写寄存器按照SJA1000的运行机制来设计,通过读写寄存器来配置CAN总线的工作模式和波特率等；位同步设计中,用状态机实现了同步段和相位缓冲段1,相位缓冲段2之间的跳转,从而完成了对采样点和发送点的捕捉；位流管理器设计主要实现数据链路层的位编码、CRC校验以及验收滤波的功能。每一部分都给出了仿真结果及详细分析。 2.利用Altera公司提供的三速以太网IP核来实现以太网协议,本文详细介绍了三速以太网IP核内部的寄存器以及内部FIFO,通过配置内部的寄存器,来最终实现以太网的功能,详细分析了以太网功能实现的仿真结果。除此之外,介绍了如何配置PHY端的接口,包括管理接口MDIO和数据接口,并用PHY芯片DP83658实现了以太网通信。 3.用SDRAM作为缓存数据的媒介来完成两个协议的转换。SDRAM的控制模块分为状态控制模块、命令控制模块和读写控制模块,其中状态控制模块主要实现控制SDRAM状态的转移,包括上电初始化和工作状态,工作状态分为读、写、自刷新等状态。命令控制模块实现对SDRAM的接口控制,通过接口信号控制SDRAM正常工作。读写控制模块,实现对SDRAM的读写控制,与SDRAM进行数据交换,本文详细介绍了每个模块的设计,并分析了两个协议转换实现的波形仿真图。本论文实现了基于FPGA的CAN协议到以太网协议的转换方案,在实际应用中具有现实意义。
[Abstract]:The combination of fieldbus technology and Ethernet technology is a hot spot in the field of industrial control. The stability of fieldbus and the flexibility of Ethernet can be realized. At present, the most widely used fieldbus is CAN bus and can bus, which has mature international standard and is regarded as one of the most promising fieldbus. In this paper, the soft core of CAN bus is designed with RTL on the FPGA platform of Altera, which is convenient for function cutting and transplanting. The protocol of Ethernet is realized by configuring triple-speed-megacore, a three-speed Ethernet IP core provided by Altera, and the development cost is reduced. Reduce the development cycle, and finally use SDRAM to store data to achieve the conversion between the two protocols. This paper has completed the following aspects of work: 1. The RTL design of CAN protocol is completed, including the design of read and write register, bit synchronization and bit stream manager. The read and write register is designed according to the running mechanism of SJA1000, and the working mode and baud rate of the CAN bus are configured by the read and write register. The state machine is used to realize the jump between the synchronization segment and the phase buffer segment 1 and the phase buffer section 2, thus the capture of the sampling point and the transmitting point is completed. The design of bit stream manager mainly realizes the function of bit coding CRC check and acceptance filter in data link layer. The simulation results and detailed analysis are given in each part. 2. The Ethernet protocol is realized by using the three-speed Ethernet IP core provided by Altera Company. This paper introduces the register inside the three-speed Ethernet IP core and the internal FIFO in detail, and finally realizes the function of Ethernet by configuring the inner register. The simulation results of Ethernet function realization are analyzed in detail. In addition, this paper introduces how to configure the interface of PHY, including management interface MDIO and data interface, and realizes Ethernet communication with PHY chip DP83658. 3. The control module of SDRAM is divided into three modules: state control module, command control module and read and write control module, in which the state control module mainly controls the transfer of SDRAM state. Including power-on initialization and working state, working state is divided into read, write, self-refresh and so on. The command control module realizes the interface control of SDRAM, and controls the normal operation of SDRAM through interface signal. The read-write control module realizes the read / write control of SDRAM and the data exchange with SDRAM. This paper introduces the design of each module in detail, and analyzes the waveform simulation diagram of two protocol conversion implementation. This paper realizes the conversion scheme from CAN protocol to Ethernet protocol based on FPGA, which has practical significance in practical application.
【学位授予单位】：北京邮电大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TP273;TP393.11

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