千兆以太网IEEE 1588协议的实现
发布时间：2018-09-12 17:30
【摘要】：随着网络技术的蓬勃发展,以太网以其协议通用性、远距离传输、灵活的网络拓扑以及不断发展的网络带宽等诸多优势,被广泛应用到测试领域。网络化自动测试系统主要针对分布式测试任务,与以太网普通应用相比,需实现控制操作的精确性和采集数据的时序关联性。IEEE 1588协议标准是网络化自动测试系统中实现测试设备及测试数据精密同步的重要方式。随着被测目标的测试复杂度和测试内容的持续增长,百兆以太网已很难适应系统对数据传输的需求,千兆以太网接口已成为未来网络化测试设备的重要形式。本文在总结当前主流的PTP(Precision Time Protocol)硬件支持方式的基础上,以Xilinx Zynq-7000 SOC作为硬件设计平台,深入分析比较了基于该硬件平台的三种PTP硬件支持方案,以通用性和可扩展性为主要考量因素,设计了一种基于PL(Programmable Logic)自研IP核实现千兆以太网下IEEE 1588协议的方案框架。本方案为搭建网络通信链路,设计了基于FMC接口的千兆以太网PHY硬件电路和屏蔽底层影响的速率选择与数据优化IP核,并开发相应的通信测试工程测试了PHY与PS(Processing System)之间的通信功能。为完成PTP硬件支持,本方案在可编程逻辑器件中设计可配置实时时钟和时间戳模块,为上层设计提供了完备的时钟调节接口,完成IEEE 1588实现亚微秒级同步精度所需的硬件支持,不要求在通信链路中配备支持硬件时间戳功能的PHY或MAC器件。上层设计采用在Linux操作系统中移植并优化PTPd开源软件并开发IP核设备驱动程序实现IEEE 1588状态机和硬件时间戳获取功能,本方案可以直接移植到包含可编程逻辑器件和支持Linux的微处理器的仪器控制架构中。在本方案的测试中,利用主从时钟输出秒脉冲信号(PPS),精确测试网络节点设备的时钟同步精度,本文从功能性和应用性两方面对本方案同步精度进行测试,分析设备时钟频率偏移、分布时钟节点数、交换机转发次数以及网络背景流量对同步精度的影响,验证了在经多次交换机转发并存在一定背景流量下的网络化测试系统中保持各网络节点设备亚微秒级同步精度的可行性。
[Abstract]:With the rapid development of network technology, Ethernet has been widely used in the field of testing for its advantages of universal protocol, long-distance transmission, flexible network topology and continuous development of network bandwidth. The networked automatic test system is mainly aimed at distributed testing tasks, compared with Ethernet applications. The precision of control operation and the timing correlation of data collected. IEEE 1588 protocol standard is an important way to realize precision synchronization of test equipment and test data in networked automatic test system. With the increasing of test complexity and test content, it is very difficult to adapt to the requirement of data transmission. Gigabit Ethernet interface has become an important form of networked test equipment in the future. On the basis of summing up the current mainstream PTP (Precision Time Protocol) hardware support methods and taking Xilinx Zynq-7000 SOC as the hardware design platform, this paper deeply analyzes and compares three kinds of PTP hardware support schemes based on this hardware platform. Taking generality and extensibility as the main consideration, a scheme framework for implementing IEEE 1588 protocol under Gigabit Ethernet based on PL (Programmable Logic) self-developed IP core is designed. In order to build the network communication link, the PHY hardware circuit of Gigabit Ethernet based on FMC interface is designed, and the rate selection and data optimization IP core of shielding the influence of the bottom layer are designed. The corresponding communication test project is developed to test the communication function between PHY and PS (Processing System). In order to complete PTP hardware support, this scheme designs configurable real-time clock and timestamp modules in programmable logic devices, provides a complete clock adjusting interface for the upper layer design, and accomplishes the hardware support required by IEEE 1588 to realize sub-microsecond synchronization precision. PHY or MAC devices that support hardware timestamp functionality are not required in communication links. The upper design adopts porting and optimizing PTPd open source software in Linux operating system and developing IP nuclear device driver to realize IEEE 1588 state machine and hardware timestamp acquisition function. This scheme can be directly transplanted to the instrument control architecture including programmable logic devices and microprocessors supporting Linux. In the test of this scheme, the clock synchronization accuracy of network node equipment is accurately tested by (PPS), which is used to output the second pulse signal from the master slave clock. The synchronization accuracy of this scheme is tested from the aspects of function and application. The effects of device clock frequency offset, number of distributed clock nodes, switch forwarding times and network background flow on synchronization accuracy are analyzed. The feasibility of maintaining the sub-microsecond synchronization accuracy of each network node equipment in the networked test system which is forwarded by multiple switches and has a certain background flow is verified.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TP393.11
，
本文编号：2239740
[Abstract]:With the rapid development of network technology, Ethernet has been widely used in the field of testing for its advantages of universal protocol, long-distance transmission, flexible network topology and continuous development of network bandwidth. The networked automatic test system is mainly aimed at distributed testing tasks, compared with Ethernet applications. The precision of control operation and the timing correlation of data collected. IEEE 1588 protocol standard is an important way to realize precision synchronization of test equipment and test data in networked automatic test system. With the increasing of test complexity and test content, it is very difficult to adapt to the requirement of data transmission. Gigabit Ethernet interface has become an important form of networked test equipment in the future. On the basis of summing up the current mainstream PTP (Precision Time Protocol) hardware support methods and taking Xilinx Zynq-7000 SOC as the hardware design platform, this paper deeply analyzes and compares three kinds of PTP hardware support schemes based on this hardware platform. Taking generality and extensibility as the main consideration, a scheme framework for implementing IEEE 1588 protocol under Gigabit Ethernet based on PL (Programmable Logic) self-developed IP core is designed. In order to build the network communication link, the PHY hardware circuit of Gigabit Ethernet based on FMC interface is designed, and the rate selection and data optimization IP core of shielding the influence of the bottom layer are designed. The corresponding communication test project is developed to test the communication function between PHY and PS (Processing System). In order to complete PTP hardware support, this scheme designs configurable real-time clock and timestamp modules in programmable logic devices, provides a complete clock adjusting interface for the upper layer design, and accomplishes the hardware support required by IEEE 1588 to realize sub-microsecond synchronization precision. PHY or MAC devices that support hardware timestamp functionality are not required in communication links. The upper design adopts porting and optimizing PTPd open source software in Linux operating system and developing IP nuclear device driver to realize IEEE 1588 state machine and hardware timestamp acquisition function. This scheme can be directly transplanted to the instrument control architecture including programmable logic devices and microprocessors supporting Linux. In the test of this scheme, the clock synchronization accuracy of network node equipment is accurately tested by (PPS), which is used to output the second pulse signal from the master slave clock. The synchronization accuracy of this scheme is tested from the aspects of function and application. The effects of device clock frequency offset, number of distributed clock nodes, switch forwarding times and network background flow on synchronization accuracy are analyzed. The feasibility of maintaining the sub-microsecond synchronization accuracy of each network node equipment in the networked test system which is forwarded by multiple switches and has a certain background flow is verified.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TP393.11
，
本文编号：2239740
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