低功耗低压差线性稳压器研究与设计

发布时间：2018-02-12 03:30

本文关键词： 低压差线性稳压器超低功耗无片外电容嵌套密勒补偿阻抗衰减缓冲器　出处：《浙江大学》2017年硕士论文　论文类型：学位论文

【摘要】：低压差线性稳压器(low-dropout regulator,LDO)具有结构简单、低噪声、低功耗以及封装尺寸小等突出优点,在便携式电子产品中作为电源转换电路得到广泛的应用。无片外电容LD0不需要外接特定的电容,也不需增加额外引脚,减小了芯片和PCB面积,从而成为近年来研究的热点。本文着重研究与设计超低功耗无片外电容LDO,首先对实现超低功耗、无片外电容LDO的几个关键问题进行了研究分析,主要针对超低功耗LDO如何分配电流、增强摆率以及无片外电容LDO如何补偿频率、改善瞬态特性等作出研究。并对低电压带隙基准的设计、高摆率缓冲器的设计、频率补偿方式的分析,以及负载调整率的改善四个方面进行了深入的理论研究和探讨。最后利用上述的理论研究,设计了输出电压为1.5 V,最大输出电流为1.5 mA,静态电流为881 nA的无片外电容LDO。该LDO主环路采用三级运放结构,将带动态偏置并联反馈结构的缓冲器作为中间级驱动PMOS功率管。使用嵌套密勒补偿方式(NMC),将低频主极点放置在第一级输出,将缓冲器输出极点和LD0输出极点作为次极点构成极点-极点追踪。芯片采用GSMC公司的130 nmCMOC工艺模型设计并经流片测试。测试结果表明:在1.6～4.2V输入电压下,输出1.5V电压,最大输出电流为1.5mA时静态电流小于881 nA。当负载电流在100 ns内由1.5 mA到0跳变时,输出电压变化小于95 mV;当电源电压在0.5 V范围内跳变时,输出电压变化小于36 mV。测试结果验证了以上设计。
[Abstract]:Low voltage differential linear regulator (LDO) has the advantages of simple structure, low noise, low power consumption and small package size. It is widely used as a power conversion circuit in portable electronic products. The off-chip capacitive LD0 does not require specific external capacitors, nor does it require additional pins, thus reducing the area of chips and PCB. In this paper, we focus on the research and design of ultra-low power off-chip capacitors. Firstly, several key issues of realizing ultra-low power consumption and off-chip capacitance LDO are studied and analyzed. This paper mainly focuses on how to distribute current in ultra-low power LDO, how to increase swing rate, how to compensate frequency of LDO without chip capacitance, how to improve transient characteristic, and how to design low voltage bandgap reference and high swing buffer. The analysis of frequency compensation mode and the improvement of load adjustment rate are discussed in four aspects. The output voltage is 1.5 V, the maximum output current is 1.5 Ma, and the static current is 881nA. The main loop of the LDO is composed of three-stage operational amplifier, the output voltage is 1.5 V, the output current is 1.5 Ma, and the static current is 881nA. The buffer with dynamic offset parallel feedback structure is used as the intermediate stage driving PMOS power transistor. The low frequency main pole is placed in the first stage output by using the nested Miller compensation method. The buffer output pole and the LD0 output pole are used as the sub-poles to constitute the pole-pole tracking. The chip is designed by GSMC 130 nmCMOC process model and tested on the wafer. The test results show that the output voltage is 1.5V at 1.6V 4.2V input voltage. When the maximum output current is 1.5 Ma, the static current is less than 881nA. when the load current changes from 1.5 Ma to 0 in 100 ns, the output voltage changes less than 95 MV, and when the supply voltage is within 0.5 V, the output voltage changes less than 95 MV. The output voltage variation is less than 36 MV. The test results verify the above design.
【学位授予单位】：浙江大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TM44

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