ESD防护研究和宽负载范围的高效DC-DC转换器设计

发布时间：2018-04-18 21:11

本文选题：静电放电(ESD) + TCAD仿真　；参考：《中国科学技术大学》2017年硕士论文

【摘要】：随着便携式电子产品的发展和增多,其对电源的需求也越来越高,提高电源管理芯片的效率是设计中需要考量的关键因素之一;同时,随着半导体工艺的进步,静电放电(ESD,Electrostatic Discharge)现象对芯片的危害日益严重。在电源管理芯片设计的过程中,研究相应的片上ESD防护器件及电路,增强全芯片静电防护能力也是非常重要的。本文基于华润上华0.5 μ m BCD工艺,对ESD防护器件进行研究设计及流片验证。利用TCAD软件Silvaco仿真平台,对比传输线脉冲(TLP,Transmission Line Pulse)测试结果进行仿真拟合;基于Smic 0.13μm CMOS工艺进行DC-DC转换器的电路设计和前仿。研究内容主要包括:1.研究ESD物理机制及器件仿真所用的物理模型。分析关键模型参数对ESD器件仿真结果的影响,主要包括掺杂浓度对触发电压的影响、结宽对维持电压的影响和载流子寿命对维持电压的影响等。通过对器件仿真中物理模型参数的调整,实现对MOS器件、可控硅(SCR,Silicon Controlled Rectifier)器件触发电压和维持电压的校准。使用同一组参数对以上共五个器件进行仿真,并与TLP测试结果比较,使触发电压与维持电压的相对误差控制在10%以内。然后运用仿真得到的物理模型参数对四个双向SCR器件进行仿真预测,并与TLP测试进行比较。2.通过研究和设计新型的ESD防护结构,改进其ESD耐压值和鲁棒性。分别进行了双向SCR结构的设计和创新以及保护环版图结构的研究和改进。并且进行了 Silvaco平台的Atlas仿真分析,流片验证以及TLP测试。测试结果表明改进后的结构可以有效改善ESD防护器件的耐压能力和鲁棒性。3.研究和设计降压型DC-DC转换器环路,依据电压模式,采用脉冲宽度调制的控制方式实现了从3.3V到1.2V的电压转化,其工作频率为1MHz。其中整个环路主要包含主电路、误差放大器、锯齿波发生器、比较器、死区控制及驱动电路、电平转换电路、电流检测电路、逻辑控制电路这几个模块。4.在控制环路中加入电流检测模块和逻辑控制电路,从而改善DC-DC转换器在负载电流变小时转换效率大幅降低的问题。通过分裂晶体管的方法并进行自动调整,减少小负载电流时工作的晶体管个数,从而降低功耗,提高效率。四组仿真结果显示,在20-500mA的宽负载范围内,采用分裂晶体管的方法之后可以将效率提高到850%以上。
[Abstract]:With the development and increase of portable electronic products, the demand for power supply is becoming higher and higher. Improving the efficiency of power management chip is one of the key factors to be considered in the design; at the same time, with the progress of semiconductor technology,Electrostatic discharge (ESD) electrostatic discharge (ESD) phenomenon is becoming more and more harmful to chips.In the process of designing the power management chip, it is also very important to study the corresponding ESD protective devices and circuits on the chip and enhance the full chip electrostatic protection capability.In this paper, the design and verification of ESD protective devices are carried out based on China Resources BCD process of 0.5 渭 m.Using TCAD software Silvaco simulation platform, comparing the test results of transmission line pulse transmission Line Pulse.The circuit design and pre-simulation of DC-DC converter based on Smic 0.13 渭 m CMOS technology are carried out.The main contents of the study include: 1.The physical mechanism of ESD and the physical model used in device simulation are studied.The influence of the key model parameters on the simulation results of ESD devices is analyzed, including the influence of doping concentration on the trigger voltage, the effect of junction width on the maintenance voltage, and the influence of carrier lifetime on the maintenance voltage.By adjusting the parameters of physical model in device simulation, the trigger voltage and maintenance voltage of MOS device, SCR device and SCR Controlled Rectifier device are calibrated.The above five devices are simulated with the same set of parameters, and compared with the TLP test results, the relative error between the trigger voltage and the maintenance voltage is controlled within 10%.Then the four bidirectional SCR devices are simulated and predicted by the physical model parameters obtained by simulation, and compared with the TLP test. 2.By studying and designing a new type of ESD protection structure, its ESD voltage resistance and robustness are improved.The design and innovation of the bidirectional SCR structure and the research and improvement of the protective ring layout structure are carried out respectively.Atlas simulation analysis, stream verification and TLP test of Silvaco platform are also carried out.The test results show that the improved structure can effectively improve the voltage resistance and robustness of ESD protective devices.The circuit of DC-DC converter is studied and designed. According to the voltage mode, the voltage conversion from 3.3 V to 1.2 V is realized by pulse width modulation. The working frequency is 1 MHz.The whole loop mainly includes main circuit, error amplifier, sawtooth wave generator, comparator, dead-time control and drive circuit, level conversion circuit, current detection circuit, logic control circuit.The current detection module and logic control circuit are added to the control loop to improve the problem of greatly reducing the conversion efficiency of the DC-DC converter in the load ER.By splitting the transistor and adjusting it automatically, the number of transistors working under small load current is reduced, thus the power consumption is reduced and the efficiency is improved.Four groups of simulation results show that the efficiency can be increased to more than 850% by using split transistor in the wide load range of 20-500mA.
【学位授予单位】：中国科学技术大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TM46

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