快速DVS响应的降压变换器设计
发布时间：2018-07-15 08:21
【摘要】：手持设备的快速发展对芯片的性能和功耗同时提出了更高要求。动态电压调节(Dynamic Voltage Scaling,DVS)正是其中一种普遍的解决方案[1]。但是有效的动态电压调节要求供电电压的变化速度足够快。LDO结构相对简单,响应速度也可以做到很快,但是存在输出动态范围小和效率低的问题。开关电源为此成为了首选,但如何做到快的DVS响应一直是开关电源很大的问题。为此,本文提出了电压模控制的具有快速DVS响应的降压变换器的设计方法,并设计和优化了一款具有5MHz开关频率的电压模控制的降压变换器。在设计方法上,本文重点分析了三型补偿中,零极点位置对环路稳定性的影响,并给出了设计实例。另外还定性地分析了降压变换器中的复极点、占空比饱和、电感电流饱和以及伪三型补偿的结构对DVS响应造成的影响。在电路设计上,本文给出了两款芯片设计方案。两款芯片采用了不同的伪三型补偿方案,其中一款芯片是对另外一款芯片的优化,并获得性能上的提升。第一款降压变换器芯片的设计基于0.13μm标准CMOS工艺。该降压变换器的输入电压范围为2.8V-3.6V,输出电压范围为1.2V-1.8V,最大负载电流1A。测试结果显示,发生DVS响应时,它的向上跟踪速度为8.3μs/V,向下跟踪速度为15μs/V。第二款降压变换器芯片的设计基于40nm标准CMOS工艺。该降压变换器的输入电压范围为2.8V-3.6V,输出电压范围为1V-2V,最大负载电流为1A。仿真结果显示,发生DVS响应时,它的向上跟踪速度为3.7μs/V,向下跟踪速度为9.3μs/V。第二款芯片采用了新的伪三型补偿拓扑,并采用非线性的方法有效抑制了下阶跃响应中可能引起的电压下冲。两款芯片都采用5MHz的开关频率,4.7μF的输出电容和1.1μH的电感。最终,该芯片验证了本文提出的具有快速DVS响应的降压变换器的设计方法。
[Abstract]:The rapid development of handheld devices requires higher performance and power consumption. Dynamic Voltage scaling (DVS) is one of the most popular solutions. However, effective dynamic voltage regulation requires that the power supply voltage change speed is fast enough. LDO structure is relatively simple, and the response speed can be achieved quickly, but there are some problems such as small dynamic range of output and low efficiency. Switching power supply has become the first choice for this, but how to achieve fast DVS response has been a big problem of switching power supply. For this reason, this paper presents the design method of a voltage-mode controlled step-down converter with fast DVS response, and designs and optimizes a voltage-mode controlled step-down converter with 5MHz switching frequency. In terms of design method, the influence of zero pole position on loop stability in three types compensation is analyzed, and a design example is given. In addition, the effects of complex poles, duty cycle saturation, inductance current saturation and pseudo-three-type compensation structure on DVS response are analyzed qualitatively. In the circuit design, this paper gives two chip design schemes. The two chips adopt different pseudo-three compensation schemes. One chip is optimized for the other chip and the performance is improved. The design of the first step-down converter is based on 0.13 渭 m standard CMOS technology. The input voltage range is 2.8V-3.6V, the output voltage range is 1.2V-1.8V, and the maximum load current is 1A. The test results show that the upward tracking speed is 8.3 渭 s / V and the downward tracking speed is 15 渭 s / V when the DVS response occurs. The design of the second step-down converter is based on 40nm standard CMOS technology. The input voltage range is 2.8V-3.6V, the output voltage range is 1V-2V, and the maximum load current is 1A. The simulation results show that the upward tracking speed is 3.7 渭 s / V and the downward tracking speed is 9.3 渭 s / V when DVS response occurs. The second chip adopts a new pseudo-three-type compensation topology, and the nonlinear method is used to effectively suppress the voltage downrush caused by the lower step response. Both chips use output capacitance of 4.7 渭 F and inductance of 1.1 渭 H with a switching frequency of 5 MHz. Finally, the chip verifies the proposed design method of the step-down converter with fast DVS response.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TM46
本文编号：2123449
[Abstract]:The rapid development of handheld devices requires higher performance and power consumption. Dynamic Voltage scaling (DVS) is one of the most popular solutions. However, effective dynamic voltage regulation requires that the power supply voltage change speed is fast enough. LDO structure is relatively simple, and the response speed can be achieved quickly, but there are some problems such as small dynamic range of output and low efficiency. Switching power supply has become the first choice for this, but how to achieve fast DVS response has been a big problem of switching power supply. For this reason, this paper presents the design method of a voltage-mode controlled step-down converter with fast DVS response, and designs and optimizes a voltage-mode controlled step-down converter with 5MHz switching frequency. In terms of design method, the influence of zero pole position on loop stability in three types compensation is analyzed, and a design example is given. In addition, the effects of complex poles, duty cycle saturation, inductance current saturation and pseudo-three-type compensation structure on DVS response are analyzed qualitatively. In the circuit design, this paper gives two chip design schemes. The two chips adopt different pseudo-three compensation schemes. One chip is optimized for the other chip and the performance is improved. The design of the first step-down converter is based on 0.13 渭 m standard CMOS technology. The input voltage range is 2.8V-3.6V, the output voltage range is 1.2V-1.8V, and the maximum load current is 1A. The test results show that the upward tracking speed is 8.3 渭 s / V and the downward tracking speed is 15 渭 s / V when the DVS response occurs. The design of the second step-down converter is based on 40nm standard CMOS technology. The input voltage range is 2.8V-3.6V, the output voltage range is 1V-2V, and the maximum load current is 1A. The simulation results show that the upward tracking speed is 3.7 渭 s / V and the downward tracking speed is 9.3 渭 s / V when DVS response occurs. The second chip adopts a new pseudo-three-type compensation topology, and the nonlinear method is used to effectively suppress the voltage downrush caused by the lower step response. Both chips use output capacitance of 4.7 渭 F and inductance of 1.1 渭 H with a switching frequency of 5 MHz. Finally, the chip verifies the proposed design method of the step-down converter with fast DVS response.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TM46
【参考文献】
相关硕士学位论文 前5条
1 杨云;适用于低噪声供电的DC-DC变换器设计[D];电子科技大学;2015年
2 龚靖;适用于PMU中DC-DC变换器片上补偿技术研究[D];电子科技大学;2013年
3 祝晓辉;适用于PMU集成的DC-DC变换器的研究与设计[D];电子科技大学;2012年
4 董晶;高性能并行计算系统中低功耗资源管理的设计与研究[D];国防科学技术大学;2009年
5 甄少伟;基于能量模型的优化PSM控制电路的设计与实现[D];电子科技大学;2008年
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