一种低功耗无片外电容LDO设计

发布时间：2018-03-23 10:19

本文选题：LDO　切入点：无片外电容　出处：《湘潭大学》2014年硕士论文

【摘要】：近年来随着便携式电子产品的迅速普及，电源管理芯片需求急剧增加。电源管理的主要目的是提高功率器件的效率，从而延长电池寿命和设备的使用时间。作为电源管理芯片中最为常见的产品，低压差线性稳压器，即LDO (low dropout regulator)，由于具有电路简单，低噪声及低功耗的优点，因此获得了广泛的应用。然而，，传统的LDO需要外接片外大电容，这样一方面增加了PCB (Printed Circuit Board)的面积；另一方面也增加了芯片的应用成本，而且也难于在SOC (System on Chip)芯片中使用。因此，无片外电容LDO成为业界关注的热点。无片外电容LDO的设计存在两个难点。首先，传统LDO环路主极点位于输出节点，利用外接大电容的等效电阻产生一个左半平面零点进行频率补偿，而无片外电容LDO的环路稳定性就必须重新考虑。其次，当LDO的负载电流发生瞬态跳变时，传统LDO主要利用片外电容进行充放电，以减小输出电压的过冲和尖峰。但对于无片外电容LDO，就必须通过提高环路的响应速度来提高瞬态响应速度，但单纯提高带宽会导致电路功耗的增加。因此，业界通常会设计一个摆率增强模块，在负载电流突变时大幅度增加误差放大器的摆率，以提高LDO的瞬态响应速度；而在正常供电时，摆率增强模块不工作，以节省功耗。本文首先在这两个方面做了深入调研，对前人提出的结构和电路进行讨论分析，在此基础上提出了新的电路结构。本论文所设计的低功耗无片外电容LDO用于为一款低功耗SIGMA-DELTA ADC中的数字电路供电。电路基于MXIC0.35μm标准CMOS工艺实现，设计输出电压3.3V，最大负载电流5mA，电源电压在2.7V~5.5V之间变化。整体电路分为带隙基准源和LDO主体电路两部分，带隙基准源为LDO提供一个与温度及电源无关的参考电压。其中带隙基准源为低功耗结构，电流消耗仅为12μA。LDO主体电路中设计了一个摆率增强模块，可以大大增加负载电流瞬态突变时误差放大器的摆率，有效提高了LDO的瞬态响应速度，从而降低了输出电压的尖峰和过冲。与相关文献中的LDO相比，本文设计的LDO其摆率增强模块具有结构简单，性能良好的特点。另外，通过将误差放大器偏置在亚阈值区，有效降低了整体电路的功耗。通过利用CADENCE仿真验证，本文设计的LDO压差电压低于100mV，LDO电路的电流消耗为31μA，负载电流瞬态突变时输出电压尖峰小于100mV，满足应用要求。
[Abstract]:In recent years, with the rapid popularization of portable electronic products, the demand for power management chips has increased dramatically. The main purpose of power management is to improve the efficiency of power devices. As the most common product in the power management chip, the low-voltage differential linear regulator, that is, the LDO low dropout regulator, has the advantages of simple circuit, low noise and low power consumption. However, the traditional LDO requires large external capacitors, which not only increase the area of PCB printed Circuit Board.On the other hand, it also increases the application cost of the chip. It is also difficult to use in SOC system on Chip chips. Therefore, off-chip capacitive LDO has become a hot spot in the industry. There are two difficulties in the design of out-of-chip capacitance LDO. Firstly, the main pole of the traditional LDO loop is located at the output node, and the equivalent resistor of the external large capacitance is used to generate a left half plane zero point to compensate the frequency. However, the loop stability of LDO without off-chip capacitance must be reconsidered. Secondly, when the load current of LDO is transient jump, the traditional LDO mainly uses off-chip capacitance to charge and discharge. In order to reduce the overshoot and spike of the output voltage, the transient response speed must be improved by increasing the response speed of the loop without the out-of-chip capacitance LDO, but the increase of the bandwidth alone will lead to the increase of the power consumption of the circuit. The industry usually designs a pendulum enhancement module to dramatically increase the swing rate of the error amplifier in the event of a sudden change in load current to improve the transient response speed of the LDO, while under normal power supply, the pendulum enhancement module does not work. In order to save power consumption, this paper first makes a thorough investigation in these two aspects, discusses and analyzes the structure and circuit proposed by the predecessors, and then puts forward a new circuit structure. The low power off-chip capacitor LDO designed in this paper is used to supply power to a digital circuit in a low-power SIGMA-DELTA ADC. The circuit is implemented on the basis of MXIC0.35 渭 m standard CMOS process. The output voltage is 3.3 V, the maximum load current is 5 Ma, and the power supply voltage varies between 2.7V~5.5V. The whole circuit is divided into two parts: bandgap reference source and LDO main circuit. The bandgap reference source provides a reference voltage independent of temperature and power supply for LDO. The bandgap reference source is a low-power structure, and the current consumption is only 12 渭 A.LDO. A pendulum enhancement module is designed in the main circuit of 12 渭 A.LDO. It can greatly increase the swing rate of the error amplifier when the load current is transient abrupt, and improve the transient response speed of the LDO effectively, thus reducing the peak and overshoot of the output voltage. Compared with the LDO in the related literature, The pendulum enhancement module designed in this paper has the characteristics of simple structure and good performance. In addition, the power consumption of the whole circuit is effectively reduced by biasing error amplifier in the sub-threshold region. The current consumption of the designed LDO circuit is 31 渭 A, and the peak of output voltage is less than 100mV when the load current is transient abrupt, which meets the requirement of application.
【学位授予单位】：湘潭大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TM44

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