基于FPGA的IEEE1588时钟同步系统的实现

发布时间：2018-06-27 01:56

本文选题：智能变电站 + 时钟同步　；参考：《大连理工大学》2015年硕士论文

【摘要】：近几年国家电网大力建设坚强智能电网,作为其构成基础的智能变电站的作用也变得越来越重要。由于智能电网具有分布式的结构特点,需要自上而下保持动作的一致性和准确性,因此要求系统内的智能变电站以及变电站中的设备运行需要在统一的时间基准之下。虽然现有的时钟同步技术很多,但都不能在保证可靠运行和节约成本的前提下提高智能变电站的对时精度。IEEE1588精确时间同步协议的提出为智能变电站提供了一种全新的时钟同步解决方案,依靠站中已存的通信网络基础可使全站实现亚微秒级同步精度。论文依据IEEE1588精确时间协议,设计了一套基于FPGA+DM9000+DP83640的时钟同步系统,用于解决智能变电站的同步问题。该系统既可以为主时钟同步其它从时钟,也可以为从时钟与主时钟同步。论文首先介绍IEEE1588协议的同步机制和相关原理,对主要的时钟同步模型、PTP时钟属性、PTP报文及数据集作了相关阐述,在此基础上,确定时钟同步系统的整体框架。在硬件部分采用FPGA作为主控芯片完成相关程序和状态机的维护；采用DM9000作为以太网控制器；采用DP83640作为物理层芯片使MII接口独立,完成时间戳信息的加盖和获取；设计GPS模块保证系统作为主时钟的精确性和可靠性。软件部分设计了PTP时钟状态机和最佳主时钟算法,用于本地时钟自主选择其在PTP系统内的主时钟,保证PTP系统的稳定运行；设计了报文处理程序,用于正确收发报文；设计了本地时钟调节程序,当本地时钟为从时钟时,通过偏移量调节和频率调节算法,完成与主时钟的精确同步；同时设计了相关硬件的驱动程序,保证时钟系统的稳定运行。论文最后给出验证方案,搭建IEEE1588时钟同步系统同步精度测试平台并实验,根据采样数据和输出秒脉冲波形的分析证明该系统设计的合理性,其同步精度可满足智能变电站的需求。
[Abstract]:In recent years, the State Grid has made great efforts to build a strong smart grid, and the role of intelligent substation, which is the basis of it, has become more and more important. Because the smart grid has the characteristic of distributed structure, it needs to keep the consistency and accuracy of the action from top to bottom, so it is required that the intelligent substation and the equipment in the substation operate under the unified time standard. Although there are a lot of clock synchronization techniques available, However, it is impossible to improve the timing accuracy of intelligent substation. IEEE1588 precise time synchronization protocol can not guarantee reliable operation and save cost, which provides a new solution for intelligent substation clock synchronization. Depending on the existing communication network, the sub-microsecond synchronization accuracy can be realized. According to IEEE1588 precise time protocol, a clock synchronization system based on FPGA DM9000 DP83640 is designed to solve the synchronization problem of intelligent substation. The system can synchronize the slave clock with the slave clock as well as the slave clock. This paper first introduces the synchronization mechanism and related principles of IEEE1588 protocol, and describes the main clock synchronization model: PTP clock attribute PTP message and data set. On this basis, it determines the overall framework of clock synchronization system. In the hardware part, FPGA is used as the main control chip to complete the maintenance of the related program and state machine, DM9000 is used as the Ethernet controller, DP83640 is used as the physical layer chip to make the Mii interface independent, and the timestamp information is stamped and obtained. GPS module is designed to ensure the accuracy and reliability of the system as the master clock. In the software part, the PTP clock state machine and the best master clock algorithm are designed, which can be used to select the master clock in the PTP system independently to ensure the stable operation of the PTP system, and the message processing program is designed to send and receive the message correctly. The local clock adjusting program is designed. When the local clock is slave clock, the accurate synchronization with the master clock is accomplished by offset adjustment and frequency adjustment algorithm. At the same time, the related hardware driver is designed to ensure the stable operation of the clock system. At the end of the paper, the verification scheme is given, and the synchronization precision test platform of IEEE1588 clock synchronization system is built and experimented. According to the analysis of sampling data and output second pulse waveform, the rationality of the system design is proved. Its synchronization accuracy can meet the needs of intelligent substation.
【学位授予单位】：大连理工大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN791;TM76

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