3GHz特性阻抗测试仪软件关键技术研究与实现
发布时间：2018-09-10 17:04
【摘要】：当前,时钟频率和数据传输速率越来越高,PCB行业为了保持信号的完整性,对特性阻抗的控制正变得越来越严格,同时,对于特性阻抗测试仪的带宽、稳定性和测量精度等指标都提出了更高的要求,对于多功能和更加智能化的特性阻抗测试仪软件的需求也更加迫切。本论文正是针对上述问题,从特性阻抗测试仪的软件关键技术入手,重点研究和实现了带宽提升算法、时钟抖动算法、增强两点校准算法。本论文的具体研究内容如下：研究和实现了带宽提升算法。首先分析了提升带宽所使用的带宽增强滤波技术和数字带宽交插复用(DBI)技术及其优缺点,然后在此基础上选择了带宽增强滤波技术作为实施方案。该方案是通过选择性的“放大”信号的高频成分,将仪器的-3dB点的频率响应提升到更高的频率,从而提高仪器的带宽,最终实现了带宽由2.3GHz提升到2.97GHz,提高了仪器的分辨率。研究和实现了时钟抖动算法。通过讨论时钟抖动的分析方法及其对信号采样的影响,进而实现了基于顺序等效采样的时钟抖动算法。该算法首先是根据采样信号及其平均信号之间的关系,统计出时钟抖动的概率密度分布并根据Tailfit抖动分离技术将总抖动(TJ)分解为确定性抖动(DJ)和随机抖动(RJ)两部分,然后统计出周期抖动(PJ)、周期间抖动(CCJ)和时间间隔误差(TIE)的峰峰值,最后以泰克TDSJTT3抖动分析软件的测试结果作为参照标准,验证了该算法的有效性,从而为检测仪器的稳定性提供了定量的分析手段,并为后续硬件设计自校准电路提供了基础。研究和实现了增强两点校准算法。该算法是在两点校准算法的基础上进行改进的,改进的地方主要包括采用波形平均的方式减小特性阻抗测试过程中的随机误差；采用自动选择最佳测量区域的方式提高校准精度；通过为每个通道配置独立的校准参数提高通道之间的独立性和一致性。最后以泰克仪器的测试结果为参照标准,验证了该算法可以有效的提高特性阻抗的测量精度。设计和实现了通道扩展以及自适应波形显示功能。将原有软件由2通道扩展为4通道,并且使测量波形能够根据被测物的实际情况自动地调整以便完整的显示在视图区的最佳位置,从而使特性阻抗测试仪更加适应大规模工业流水线混合智能化测试。本文的最后对软件的功能、性能和异常情况进行了测试并分析了测试结果。
[Abstract]:At present, in order to maintain the integrity of signal, the control of characteristic impedance is becoming more and more strict in the PCB industry with the increasing clock frequency and data transmission rate. At the same time, the bandwidth of the characteristic impedance tester is becoming more and more strict. The requirements of stability and measurement accuracy are higher, and the requirement of multi-function and more intelligent characteristic impedance tester software is more urgent. Aiming at the above problems, this paper starts with the key software technology of the characteristic impedance tester, and focuses on the research and implementation of bandwidth enhancement algorithm, clock jitter algorithm and enhanced two-point calibration algorithm. The main contents of this thesis are as follows: the bandwidth enhancement algorithm is studied and implemented. Firstly, the bandwidth enhancement filtering technology and digital bandwidth interleaved multiplexing (DBI) technology are analyzed, and then the bandwidth enhancement filtering technology is selected as the implementation scheme. By selectively "amplifying" the high-frequency component of the signal, the frequency response of -3dB point of the instrument is raised to a higher frequency, thus the bandwidth of the instrument is increased, and the bandwidth is raised from 2.3GHz to 2.97GHz, and the resolution of the instrument is improved. The clock jitter algorithm is studied and implemented. By discussing the analysis method of clock jitter and its influence on signal sampling, a clock jitter algorithm based on sequential equivalent sampling is implemented. Firstly, according to the relationship between the sampled signal and its average signal, the probability density distribution of clock jitter is calculated, and the total jitter (TJ) is decomposed into deterministic jitter (DJ) and random jitter (RJ) according to Tailfit jitter separation technique. Then the peak value of jitter (CCJ) and interval error (TIE) during the period jitter (PJ), cycle is calculated. Finally, the test results of Teke TDSJTT3 jitter analysis software are used as the reference standard to verify the validity of the algorithm. It provides a quantitative analysis method for the stability of the instrument and provides a basis for the subsequent hardware design of the self-calibrating circuit. An enhanced two-point calibration algorithm is studied and implemented. The algorithm is improved on the basis of two-point calibration algorithm. The improvement mainly includes using waveform averaging to reduce the random error in the process of characteristic impedance testing. The calibration accuracy is improved by automatically selecting the best measurement area, and the independence and consistency of each channel is improved by configuring independent calibration parameters for each channel. Finally, using the test results of the Tak instrument as the reference standard, it is verified that the algorithm can effectively improve the measurement accuracy of the characteristic impedance. The function of channel expansion and adaptive waveform display is designed and implemented. The original software is extended from 2 channels to 4 channels, and the measurement waveform can be automatically adjusted according to the actual situation of the object under test in order to display the best position in the view area. Thus, the characteristic impedance tester is more suitable for large scale industrial pipeline hybrid intelligent test. Finally, the function, performance and exception of the software are tested and the test results are analyzed.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TM934.7
本文编号：2235072
[Abstract]:At present, in order to maintain the integrity of signal, the control of characteristic impedance is becoming more and more strict in the PCB industry with the increasing clock frequency and data transmission rate. At the same time, the bandwidth of the characteristic impedance tester is becoming more and more strict. The requirements of stability and measurement accuracy are higher, and the requirement of multi-function and more intelligent characteristic impedance tester software is more urgent. Aiming at the above problems, this paper starts with the key software technology of the characteristic impedance tester, and focuses on the research and implementation of bandwidth enhancement algorithm, clock jitter algorithm and enhanced two-point calibration algorithm. The main contents of this thesis are as follows: the bandwidth enhancement algorithm is studied and implemented. Firstly, the bandwidth enhancement filtering technology and digital bandwidth interleaved multiplexing (DBI) technology are analyzed, and then the bandwidth enhancement filtering technology is selected as the implementation scheme. By selectively "amplifying" the high-frequency component of the signal, the frequency response of -3dB point of the instrument is raised to a higher frequency, thus the bandwidth of the instrument is increased, and the bandwidth is raised from 2.3GHz to 2.97GHz, and the resolution of the instrument is improved. The clock jitter algorithm is studied and implemented. By discussing the analysis method of clock jitter and its influence on signal sampling, a clock jitter algorithm based on sequential equivalent sampling is implemented. Firstly, according to the relationship between the sampled signal and its average signal, the probability density distribution of clock jitter is calculated, and the total jitter (TJ) is decomposed into deterministic jitter (DJ) and random jitter (RJ) according to Tailfit jitter separation technique. Then the peak value of jitter (CCJ) and interval error (TIE) during the period jitter (PJ), cycle is calculated. Finally, the test results of Teke TDSJTT3 jitter analysis software are used as the reference standard to verify the validity of the algorithm. It provides a quantitative analysis method for the stability of the instrument and provides a basis for the subsequent hardware design of the self-calibrating circuit. An enhanced two-point calibration algorithm is studied and implemented. The algorithm is improved on the basis of two-point calibration algorithm. The improvement mainly includes using waveform averaging to reduce the random error in the process of characteristic impedance testing. The calibration accuracy is improved by automatically selecting the best measurement area, and the independence and consistency of each channel is improved by configuring independent calibration parameters for each channel. Finally, using the test results of the Tak instrument as the reference standard, it is verified that the algorithm can effectively improve the measurement accuracy of the characteristic impedance. The function of channel expansion and adaptive waveform display is designed and implemented. The original software is extended from 2 channels to 4 channels, and the measurement waveform can be automatically adjusted according to the actual situation of the object under test in order to display the best position in the view area. Thus, the characteristic impedance tester is more suitable for large scale industrial pipeline hybrid intelligent test. Finally, the function, performance and exception of the software are tested and the test results are analyzed.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TM934.7
【参考文献】
相关期刊论文 前1条
1 秦庚 ,邬宁彪 ,李小明;印制电路板特性阻抗的测试技术[J];印制电路信息;2004年11期
，本文编号：2235072
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