并联均流降压型DC-DC转换器的设计
发布时间：2019-01-06 13:11
【摘要】：随着电子技术的高速发展和国家对电子产业发展的需要,开关电源的需求量得到了巨大的增长,人们对电源管理类芯片的性能和功能也提出了更多和更高的要求。小型化、高效率、抗EMI、少的外围器件、低压大电流等成为了电源芯片设计中日益重要的研究课题。本论文是基于电源发展趋势的需求并结合实验室现有科研成果,研究可多路并联输出的同步降压型DC-DC转换器芯片组的设计及实现。本文详细分析了Buck型DC-DC转换器的基本工作原理,对其稳态下各输出点的工作波形做了详细的分析,对其传输关系做完整的推导,对芯片组并联使用时最优控制方案和减小纹波方法理论上做了简要的阐述。在此基础上设计了一款可实现多路并联输出的低纹波率同步降压型转换器。该转换器采用PWM调制的峰值电流模控制方式,提高了系统的瞬态反应速度,且具有输出电感较小、补偿电路简单、增益带宽大、易于均流等优点。此款芯片可以实现单通道的大电流输出和两款该芯片并联的双通道输出,或者更多该同类型芯片并联实现更大电流的输出。设计中充分考虑了多个DC-DC转换器并联时,如何实现芯片组之间电流的均分,以减轻热损耗,改善系统的反应速度,延长芯片组中各子模块的寿命。芯片内部集成了锁相环电路和分频电路,可以使芯片在多相模式下工作,以有效的减小在多个芯片并联使用时所需的大容量电容,降低大电流工作下输出和输入电压纹波的大小。而且内部集成的锁相环同步电路和采用的主从均流控制方式,能够有效的实现输出电流的均分。对于芯片工作在轻负载时,可以根据客户在输出电压纹波大小和效率之间的需要,选择两种不同的工作方式:强制脉冲宽度调制模式(FCCM)或脉冲跳变调制模式(PSM)。针对芯片宽输入和宽输出范围,芯片设计了一种二次斜坡补偿技术,相对于普通的一次线性斜坡补偿,进一步提高了芯片的整体的带载能力以及消除了占空比大于50%时出现的亚谐波振荡、开环不稳定和对噪声比较敏感等缺点。同时设计中采用了动态箝位电路,对误差放大器的输出端采用了动态电压进行限幅,相对于固定的箝位电压,有效的避免了斜坡补偿对芯片带载能力的影响。此外,芯片内部还集成了欠压保护、过压保护、过流保护、外部软启动电路等多种功能。论文对该款芯片选用BCD工艺的原因也做了说明,针对芯片外围器件的选择和影响芯片工作效率的因素,论文同样做了比较详细的分析。本文研究的可实现多路并联均流降压型DC-DC转换器芯片组是基于0.35um BCD工艺设计,在Cadence下完成了芯片子模块电路和整体功能的仿真。单个芯片输入电压范围4.5V~26.5V,单通道最大可以拉8A负载电流,双通道并联组成的输出,能使输出电流达到16A,单款芯片效率可达95%,符合设计要求。
[Abstract]:With the rapid development of electronic technology and the development of national electronic industry, the demand for switching power supply has been greatly increased, and the performance and function of power management chips have been put forward more and higher requirements. Miniaturization, high efficiency, low EMI, resistance, low voltage and high current have become increasingly important research topics in power chip design. This paper is based on the development trend of power supply and combined with the existing scientific research results of the laboratory to study the design and implementation of synchronous step-down DC-DC converter chipset with multi-parallel output. In this paper, the basic working principle of Buck type DC-DC converter is analyzed in detail, the working waveform of each output point in steady state is analyzed in detail, and the transmission relation is deduced. The optimal control scheme and the method of reducing ripple in parallel operation of chipset are briefly described in theory. Based on this, a low ripple rate synchronous step-down converter is designed. The converter adopts the peak current mode control method of PWM modulation, which improves the transient response speed of the system, and has the advantages of small output inductance, simple compensation circuit, large gain bandwidth and easy current sharing. This chip can realize the high current output of single channel and the double channel output of two parallel chips, or more of the same type chip can realize larger current output in parallel. In order to reduce the heat loss, improve the reaction speed of the system and prolong the life of each sub-module of the chipset, the design takes full account of how to realize the equalization of current between the chipsets when several DC-DC converters are connected in parallel. The PLL circuit and the frequency divider circuit are integrated inside the chip, which can make the chip work in the multi-phase mode, so as to effectively reduce the large capacity capacitors needed for the parallel use of multiple chips. Reduce the output and input voltage ripple size under high current operation. The internal integrated PLL synchronization circuit and the master-slave current sharing control method can effectively realize the average output current distribution. When the chip works under light load, two different modes of operation can be selected according to the customer's demand between output voltage ripple size and efficiency: forced pulse width modulation mode (FCCM) or pulse jump modulation mode (PSM). For the wide input and wide output range of the chip, a secondary ramp compensation technique is designed, which is relative to the common linear ramp compensation. It further improves the overall load capacity of the chip and eliminates the shortcomings of sub-harmonic oscillation, open-loop instability and sensitivity to noise when the duty cycle is larger than 50. At the same time, the dynamic clamping circuit is used in the design, and the dynamic voltage is used to limit the output of the error amplifier. Compared with the fixed clamping voltage, the slope compensation can effectively avoid the influence of the ramp compensation on the chip's load capacity. In addition, there are many functions such as under-voltage protection, over-current protection, external soft start circuit and so on. This paper also explains the reason why the chip uses BCD technology. The paper also makes a detailed analysis on the choice of chip peripheral devices and the factors that affect the efficiency of the chip. In this paper, the chipset of DC-DC converter with parallel current and voltage sharing is designed based on 0.35um BCD technology. The circuit and the whole function of the chip are simulated under Cadence. The input voltage of a single chip ranges from 4.5 V to 26.5V, and the maximum load current of 8A can be pulled by a single channel. The output current of two parallel channels can reach 16A, and the efficiency of a single chip can reach 95A, which meets the design requirements.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TM46
本文编号：2402828
[Abstract]:With the rapid development of electronic technology and the development of national electronic industry, the demand for switching power supply has been greatly increased, and the performance and function of power management chips have been put forward more and higher requirements. Miniaturization, high efficiency, low EMI, resistance, low voltage and high current have become increasingly important research topics in power chip design. This paper is based on the development trend of power supply and combined with the existing scientific research results of the laboratory to study the design and implementation of synchronous step-down DC-DC converter chipset with multi-parallel output. In this paper, the basic working principle of Buck type DC-DC converter is analyzed in detail, the working waveform of each output point in steady state is analyzed in detail, and the transmission relation is deduced. The optimal control scheme and the method of reducing ripple in parallel operation of chipset are briefly described in theory. Based on this, a low ripple rate synchronous step-down converter is designed. The converter adopts the peak current mode control method of PWM modulation, which improves the transient response speed of the system, and has the advantages of small output inductance, simple compensation circuit, large gain bandwidth and easy current sharing. This chip can realize the high current output of single channel and the double channel output of two parallel chips, or more of the same type chip can realize larger current output in parallel. In order to reduce the heat loss, improve the reaction speed of the system and prolong the life of each sub-module of the chipset, the design takes full account of how to realize the equalization of current between the chipsets when several DC-DC converters are connected in parallel. The PLL circuit and the frequency divider circuit are integrated inside the chip, which can make the chip work in the multi-phase mode, so as to effectively reduce the large capacity capacitors needed for the parallel use of multiple chips. Reduce the output and input voltage ripple size under high current operation. The internal integrated PLL synchronization circuit and the master-slave current sharing control method can effectively realize the average output current distribution. When the chip works under light load, two different modes of operation can be selected according to the customer's demand between output voltage ripple size and efficiency: forced pulse width modulation mode (FCCM) or pulse jump modulation mode (PSM). For the wide input and wide output range of the chip, a secondary ramp compensation technique is designed, which is relative to the common linear ramp compensation. It further improves the overall load capacity of the chip and eliminates the shortcomings of sub-harmonic oscillation, open-loop instability and sensitivity to noise when the duty cycle is larger than 50. At the same time, the dynamic clamping circuit is used in the design, and the dynamic voltage is used to limit the output of the error amplifier. Compared with the fixed clamping voltage, the slope compensation can effectively avoid the influence of the ramp compensation on the chip's load capacity. In addition, there are many functions such as under-voltage protection, over-current protection, external soft start circuit and so on. This paper also explains the reason why the chip uses BCD technology. The paper also makes a detailed analysis on the choice of chip peripheral devices and the factors that affect the efficiency of the chip. In this paper, the chipset of DC-DC converter with parallel current and voltage sharing is designed based on 0.35um BCD technology. The circuit and the whole function of the chip are simulated under Cadence. The input voltage of a single chip ranges from 4.5 V to 26.5V, and the maximum load current of 8A can be pulled by a single channel. The output current of two parallel channels can reach 16A, and the efficiency of a single chip can reach 95A, which meets the design requirements.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TM46
【参考文献】
相关期刊论文 前2条
1 毕超;肖飞;谢桢;陈明;;交错并联技术在并联DC-DC变换器纹波抑制中的分析与应用[J];电气自动化;2013年04期
2 路秋生;电流型变换器工作原理和斜坡补偿[J];仪器仪表学报;2001年S2期
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