PMU中高性能DC-DC变换器的设计
发布时间：2019-01-09 16:45
【摘要】：近年来,随着半导体工艺的高速发展,CMOS的最小线宽已经进入纳米量级,相同尺寸的芯片能集成越来越多的晶体管,片上系统SoC(System on Chip)成为行业发展的主流。在消费类市场,随着便携式电子产品的快速普及,人们对电源类芯片也提出更高,更复杂的要求。因此设计高集成度,高性能的PMU集成芯片成为行业发展趋势,也是行业的紧迫任务。本文设计了一款适用于PMU(Power Management Unit)集成的DC-DC变换器芯片。针对如何提高DC-DC变换器的关键性能(包括线性调整率,负载调整率,电源抑制比,效率,动态响应速度),提出了电压前馈电路,全差分伪三型补偿电路,双模控制电路,自校正电路等技术手段。其中电压前馈电路使得系统传输函数不再受输入电压变化的影响,提高系统线性调整率。全差分伪三型补偿电路,将一路带通信号和一路低通信号叠加,产生类似传统三型补偿电路的频率响应,极大减小所需要的电容电阻值,另外全差分结构提高了电源抑制比,有效抑制了Buck变换器工作时电源噪声对控制电路的影响。PWM/PSM双模技术兼顾系统的负载调整率和效率,确保了重载PWM模式下的负载调整率,在轻载PSM模式下提高了系统的效率。自校正电路直接调节占空比大小,以使输出电压尽快恢复到基准电压±1%范围内,有助于提高变换器的负载调整率和DVS响应速度。通过仿真验证,本文设计的DC-DC变换器工作频率为2MHz;其输入电压为2.7V~4.2V;采用DVS技术,输出电压0.7V~1.5V,步进25mV可调;输出电流可达1A;采用PSM/PWM双模控制技术,在轻载下进入PSM模式,效率可达80%以上,在重载下进入PWM模式,效率可达90%以上;利用全差分伪三型补偿与自校正电路,重载下负载调整率小于1%;利用电压前馈电路,线性调整率小于1%。在1 kHz频率以内,控制电路电源抑制比提高到116dB。
[Abstract]:In recent years, with the rapid development of semiconductor technology, the minimum linewidth of CMOS has entered the nanometer order of magnitude, the chip of the same size can integrate more and more transistors, and the on-chip system SoC (System on Chip) has become the mainstream of the industry. In the consumer market, with the rapid popularity of portable electronic products, people also put forward higher and more complex requirements for power chips. Therefore, the design of high integration and high performance PMU integrated chips has become the trend of industry development, and is also an urgent task of the industry. A DC-DC converter chip suitable for PMU (Power Management Unit) integration is designed in this paper. Aiming at how to improve the key performance of DC-DC converter (including linear adjustment rate, load adjustment rate, power supply rejection ratio, efficiency, dynamic response speed), the voltage feedforward circuit, fully differential pseudo-three-type compensation circuit and dual-mode control circuit are proposed. Self-tuning circuit and other technical means. The voltage feedforward circuit makes the system transmission function no longer affected by the input voltage change and improves the linear adjustment rate of the system. The fully differential pseudo-three-type compensation circuit superposes one pass signal and one low-pass signal to produce a frequency response similar to that of the traditional three-type compensation circuit, which greatly reduces the required capacitance resistance. In addition, the fully differential structure improves the power supply rejection ratio. The effect of power noise on the control circuit of Buck converter is effectively suppressed. The load adjustment rate and efficiency of the system are considered in PWM/PSM dual-mode technology, which ensures the load adjustment rate in heavy-load PWM mode. The efficiency of the system is improved under the light load PSM mode. The self-tuning circuit directly adjusts the duty cycle in order to restore the output voltage to 卤1% of the reference voltage as soon as possible, which is helpful to improve the load adjustment rate and the DVS response speed of the converter. The simulation results show that the operating frequency of the DC-DC converter designed in this paper is 2 MHz, the input voltage is 2. 7 V / 4. 2 V, the output voltage is 0. 7 V / 1. 5 V, the step 25mV is adjustable, the output current is up to 1 A by using DVS technology. Using PSM/PWM dual-mode control technology, the efficiency of entering PSM mode under light load can reach more than 80%, and the efficiency of entering PWM mode under heavy load can reach more than 90%. By using fully differential pseudo-triple-type compensation and self-tuning circuit, the load adjustment rate under heavy load is less than 1 and the linear adjustment rate is less than 1 by using voltage feedforward circuit. Within 1 kHz frequency, the power supply rejection ratio of the control circuit is increased to 116 dB.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TM46
本文编号：2405876
[Abstract]:In recent years, with the rapid development of semiconductor technology, the minimum linewidth of CMOS has entered the nanometer order of magnitude, the chip of the same size can integrate more and more transistors, and the on-chip system SoC (System on Chip) has become the mainstream of the industry. In the consumer market, with the rapid popularity of portable electronic products, people also put forward higher and more complex requirements for power chips. Therefore, the design of high integration and high performance PMU integrated chips has become the trend of industry development, and is also an urgent task of the industry. A DC-DC converter chip suitable for PMU (Power Management Unit) integration is designed in this paper. Aiming at how to improve the key performance of DC-DC converter (including linear adjustment rate, load adjustment rate, power supply rejection ratio, efficiency, dynamic response speed), the voltage feedforward circuit, fully differential pseudo-three-type compensation circuit and dual-mode control circuit are proposed. Self-tuning circuit and other technical means. The voltage feedforward circuit makes the system transmission function no longer affected by the input voltage change and improves the linear adjustment rate of the system. The fully differential pseudo-three-type compensation circuit superposes one pass signal and one low-pass signal to produce a frequency response similar to that of the traditional three-type compensation circuit, which greatly reduces the required capacitance resistance. In addition, the fully differential structure improves the power supply rejection ratio. The effect of power noise on the control circuit of Buck converter is effectively suppressed. The load adjustment rate and efficiency of the system are considered in PWM/PSM dual-mode technology, which ensures the load adjustment rate in heavy-load PWM mode. The efficiency of the system is improved under the light load PSM mode. The self-tuning circuit directly adjusts the duty cycle in order to restore the output voltage to 卤1% of the reference voltage as soon as possible, which is helpful to improve the load adjustment rate and the DVS response speed of the converter. The simulation results show that the operating frequency of the DC-DC converter designed in this paper is 2 MHz, the input voltage is 2. 7 V / 4. 2 V, the output voltage is 0. 7 V / 1. 5 V, the step 25mV is adjustable, the output current is up to 1 A by using DVS technology. Using PSM/PWM dual-mode control technology, the efficiency of entering PSM mode under light load can reach more than 80%, and the efficiency of entering PWM mode under heavy load can reach more than 90%. By using fully differential pseudo-triple-type compensation and self-tuning circuit, the load adjustment rate under heavy load is less than 1 and the linear adjustment rate is less than 1 by using voltage feedforward circuit. Within 1 kHz frequency, the power supply rejection ratio of the control circuit is increased to 116 dB.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TM46
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