功率STI-LDMOS器件热载流子退化机理与寿命模型研究

发布时间：2017-12-27 05:28

本文关键词：功率STI-LDMOS器件热载流子退化机理与寿命模型研究　出处：《东南大学》2016年硕士论文　论文类型：学位论文

【摘要】：浅槽隔离(STI)工艺因其无鸟嘴、集成度高及隔离能力强等优点成为深亚微米功率集成电路领域的主流,功率STI-LDMOS器件也因此成为应用最广的小尺寸功率器件。然而器件尺寸缩小并未带来工作电压的等比例缩小,热载流子效应导致的器件退化进一步加剧,传统功率LDMOS器件热载流子效应的研究结论已不能适用于功率STI-LDMOS器件。因此有必要对其新的退化机理及相关寿命模型展开深入研究。本文首先利用I/V退化测试系统和Sentaurus TCAD仿真平台研究并揭示了功率STI-LDMOS器件的退化机理：中栅压高漏压条件下器件退化由靠近源极的STI拐角处的界面态主导,而高栅压高漏压条件下器件退化由靠近漏极的STI拐角处的界面态主导。另外,研究发现温度越高,器件线性区漏极电流Idlin的退化越大,这是因为温度升高降低了器件的阈值电压,从而增大了电流,提高了器件内部的碰撞电离率,加剧了器件退化。随后,探讨了器件寿命的考核方法,包括最坏应力条件的选取和器件性能参数的监测方法,进而根据退化机理和考核标准建立了器件电学参数的退化寿命模型,通过验证发现模型的误差在10%以内。最后,基于上述退化机理和寿命模型对器件进行了优化,研究发现：增大沟道长度、增大栅极场板长度,减小STI侧壁的倾斜角或增大STI拐角的曲率半径均可提升器件的热载流子可靠性。同时,还提出了槽栅结构、P型埋层结构与分离栅结构等三种具有高热载流子可靠性的新型功率STI-LDMOS器件结构。本文的成果对深亚微米功率器件的热载流子效应研究以及高可靠性器件设计具有借鉴意义。
[Abstract]:Shallow trench isolation (STI) technology because of its advantages of no bill, high integration and isolation ability has become the mainstream of deep submicron integrated circuit power field, power STI-LDMOS device has become a small size power device is the most widely used. However, the size reduction of the device does not bring the equal voltage reduction of the working voltage. The degradation of the device caused by the hot carrier effect is further intensified. The conclusion of the hot carrier effect of the conventional power LDMOS device is no longer applicable to power STI-LDMOS devices. Therefore, it is necessary to carry out a thorough study of its new degradation mechanism and related life model. This paper use the I/V degradation test research system and Sentaurus TCAD simulation platform and degradation mechanism of power STI-LDMOS devices that the gate voltage in high leakage pressure conditions by device degradation near the source STI interface state at the corner of the leading, and the high voltage interface state high leakage pressure conditions back from near the drain STI device at the corner of the leading. In addition, it is found that the higher the temperature is, the greater the degradation of Idlin is. The higher the temperature is, the lower the threshold voltage of the device, which will increase the current, increase the internal ionization rate and intensify the device degradation. Then, discusses the evaluation method of life of the device, the monitoring method including the selection of the worst stress conditions and device performance parameters, and then according to the electrical parameters of the device degradation life model established degradation mechanism and assessment standards, through verification model of the error is less than 10%. Finally, based on the above degradation mechanism and life model, the device is optimized. It is found that increasing the channel length, increasing the gate field length, reducing the inclination angle of the STI sidewall or increasing the radius of curvature of the STI corner can enhance the hot carrier reliability of the device. At the same time, three new power STI-LDMOS devices with high thermal carrier reliability are proposed, such as slot structure, P type buried layer structure and separation grid structure. The results of this paper are useful for the research of the hot carrier effect of deep submicron power devices and the design of high reliability devices.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN386

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