高线性度电流模混频器及电流模可变增益放大器的设计

发布时间：2018-01-03 10:08

本文关键词：高线性度电流模混频器及电流模可变增益放大器的设计　出处：《东南大学》2015年硕士论文　论文类型：学位论文

【摘要】：随着模拟广播的数字化发展,研究兼容基于全球数字广播(DRM, Digital Radio Mondiale)与数字音频广播(DAB, Digital Audio Broadcasting)两种广播标准的接收机芯片将极大地提升我国在无线通信芯片的地位,具有重大意义。DRM/DAB接收机芯片架构为两次变频低中频结构,从第二中频混频器开始将电压信号转换为电流信号。本文研究的内容是应用于DRM/DAB接收机的第二中频CMixer(Currrent-mode Mixer)即电流模混频器和CPGA(Current-Mode Programmable Gain Amplifier)即电流模数字可编程增益放大器电路。CMixer的输入为35.452MHz的第一中频电压信号,本振信号为37.5MHz电压信号,输出为2.048MHz第二中频电流信号。混频器采用动态偏置跨导将电压信号转为电流信号,然后经过无源开关混频器混频,最后经过电流模放大器推动输出。其中无源开关级本振偏置为动态偏置结构,克服电压、工艺角、温度的影响。CPGA的输入输出信号均为电流信号,中心频率为2.048MHz,带宽为1.536MHz。本文的电流放大采用电流模技术,采用电流求和网络实现电流增益。直流失调消除电路抑制直流增益,减少电路的失配带来的不稳定因素。采用有源电阻代替无源电阻,减少版图面积。数字控制逻辑采用译码器译码,减少测试焊盘数量。两个模块电路均采用中芯国际SMIC 0.18μm RFCMOS工艺进行仿真验证,并进行了流片、测试,测试结果基本满足设计要求。同时,分析了测试结果,对进一步工作提出了建议。
[Abstract]:With the development of digital analog broadcasting, digital broadcasting based on global compatibility study (DRM Digital, Radio Mondiale) and digital audio broadcasting (DAB Digital, Audio Broadcasting) receiver chip two broadcast standard will greatly enhance China's position in the wireless communication chip,.DRM/DAB receiver chip architecture is of great significance for two times frequency low frequency the structure, converting the voltage signal to current signal from the beginning of the second frequency mixer. The content of this paper is second if CMixer is applied to the DRM/DAB receiver (Currrent-mode Mixer) is the current mode mixer and CPGA (Current-Mode Programmable Gain Amplifier) is a digital input current mode programmable gain amplifier circuit.CMixer for the first intermediate frequency voltage signal of 35.452MHz. The vibration signal is 37.5MHz voltage signal, the output for the 2.048MHz second frequency mixer using current signal. Dynamic bias voltage signal to current transconductance signal, and then through the passive switch mixer mixing, after the current mode amplifier to drive output. The passive switch level oscillator bias for the dynamic bias voltage, overcome the influence of temperature, process angle,.CPGA input and output signal to current signal, the center frequency is 2.048MHz, bandwidth for the current 1.536MHz. amplification using the current mode, the current implementation of the current gain summing network. DC offset cancellation circuit to suppress DC gain, reduce instability circuit mismatch. The resistance of the active instead of passive resistance, reduce the layout area. The digital control logic decoder, reduce the test pad number two. A module circuit uses SMIC SMIC 0.18 m RFCMOS process simulation, and implemented, tested, the test results satisfy the design requirements. At the same time, the test results were analyzed and suggestions for further work were put forward.

【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN722;TN773

【相似文献】