衬底触发SCR-LDMOS堆叠结构的高压ESD特性研究

发布时间：2018-01-05 14:30

本文关键词：衬底触发SCR-LDMOS堆叠结构的高压ESD特性研究　出处：《电子科技大学》2015年硕士论文　论文类型：学位论文

【摘要】：ESD(Electrostatic Discharge,静电泄放)是集成电路行业中最重要的可靠性问题之一,每年将近40%的失效IC芯片是由ESD/EOS(电过载)引起的。随着半导体工艺的发展,特别是高压智能功率技术的普遍应用,使得高压ESD问题越来越突出。而高压ESD最突出的问题是维持电压过低,在上电情况下发生ESD,容易导致闩锁效应。本文首先介绍了ESD的基本工作原理和几种常见的ESD器件,讨论了CMOS闩锁效应、影响CMOS闩锁效应的参数以及闩锁效应与ESD的关系和区分,分析了高压ESD的闩锁效应问题,指出了提高维持电压是解决闩锁效应的有效的方法,并给出了几种提高维持电压的方法和案例。其次,提出了一种新型的用于高压ESD防护的自触发STSCR-LDMOS(Substrate Trigger Semiconductor Control Rectifier-Laterally Diffused Metal Oxide Semiconductor,衬底触发硅控晶闸管-横向双扩散金属半导体场效应管)堆叠结构,解释了其工作机理,并采用多脉冲(TLP Transmission Line Pulse,传输线)仿真方法进行仿真和分析。分析结果表明自触发STSCR-LDMOS堆叠结构的维持电压随着堆叠个数的增加而成倍的增加,而触发电压主要取决于STSCR-LDMOS1的触发电压,以触发电阻为100Ω时为例,当堆叠个数从1增加到4,维持电压从6.9V增加到25.4V,而触发电压只从71.6V增加到了79.7V。同时分析了STSCR-LDMOS的阴极N+与P+之间的距离L、P-trig端P+与阴极N+之间的距离L0以及触发电阻对堆叠结构的维持电压和触发电压的影响,给出了距离L、L0和触发电阻的最佳值。最后,提出了LDMOS触发STSCR-LDMOS堆叠结构,这是自触发STSCRLDMOS堆叠结构的一种优化结构,仿真分析表明,LDMOS触发STSCR-LDMOS堆叠结构具有更小的触发电压,且其受触发电阻的影响更小,因此可以堆叠更多的STSCR-LDMOS单元,以获得更高的维持电压。以触发电阻为50Ω时为例,当堆叠个数从1增加到6时,维持电压从7.4V增加到40.5V,而触发电压从70.1V只增加到了75.3V。
[Abstract]:ESD (Electrostatic Discharge, electrostatic discharge) is one of the most important reliability problems in integrated circuit industry, IC chip failure nearly 40% a year by ESD/EOS (electrical overload caused). With the development of semiconductor technology, especially the common voltage intelligent power technology, the high-voltage ESD problem is becoming more and more serious. The most prominent problem is the maintenance of high voltage ESD voltage is too low, ESD occurred in the case, easy to cause the latch up effect. This paper first introduces the basic working principle of common ESD devices and several ESD, the CMOS latch effect is discussed, parameters affecting the CMOS latch effect and latch up effect and the relationship between the ESD and the distinguish analysis of high-pressure ESD latch effect problem, and points out that to improve the sustain voltage is an effective way to solve the latch up effect, and gives several improving methods and case maintenance voltage. Secondly, proposed a new Type for self triggering STSCR-LDMOS high voltage protection of ESD (Substrate Trigger Semiconductor Control Rectifier-Laterally Diffused Metal Oxide Semiconductor, the substrate triggered silicon controlled thyristor - lateral double diffused metal oxide semiconductor field effect transistor) stack structure, explains its working mechanism, and the use of multi pulse (TLP Transmission Line Pulse, transmission line simulation method) the simulation and analysis. The analysis results show that the self triggering STSCR-LDMOS stack structure to maintain the voltage increases with the number of stacked and multiplied, and the trigger voltage depends mainly on the STSCR-LDMOS1 trigger voltage to trigger a resistor of 100 as an example, when the stack number increased from 1 to 4, to maintain the voltage increased from 6.9V to 25.4V however, only the trigger voltage is increased from 71.6V to 79.7V. were analyzed between N+ and P+ STSCR-LDMOS cathode distance L between P-trig P+ and the cathode end distance of N+ From the L0 and trigger resistance effects on maintaining the structure of the stack voltage and trigger voltage, given the distance of L, L0 and the optimal trigger resistance value. Finally, the LDMOS trigger STSCR-LDMOS stack structure, which is self triggering an optimized structure of STSCRLDMOS stack structure, simulation results show that LDMOS STSCR-LDMOS has triggered a stacked structure the smaller the trigger voltage, and the influence of smaller trigger resistance, so it can be stacked STSCR-LDMOS unit more, to get to maintain higher voltage to trigger a resistor of 50. For example, when the stack number increased from 1 to 6, to maintain the voltage increased from 7.4V to 40.5V, and the trigger voltage from 70.1V only increased to 75.3V.

【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN405

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