高速低功耗逐次逼近模数转换器的研究与设计

发布时间：2018-01-05 19:22

本文关键词：高速低功耗逐次逼近模数转换器的研究与设计　出处：《南京邮电大学》2015年硕士论文　论文类型：学位论文

【摘要】：可穿戴移动设备、红外传感器以及无线传感器网络的迅速发展对电子系统的小型化提出了更高的要求,而模数转换器是系统中必不可少的部分,其性能直接影响着整个系统的性能。而逐次逼近模数转换器因其功耗低、面积小、速度适中等特点,长期以来获得了广泛的运用,因此其设计技术日益受到关注。本文首先分析了模数转换器的常见结构及其工作原理,并对它们各自的优缺点进行了对比,同时从动态功耗和非线性参数INL/DNL角度对现有的逐次逼近模数转换器里的电容阵列进行了分析与对比,在此基础上完成了一种6位120MS/s的逐次逼近型模数转换器电路的设计。通过对三明治-插指混合型结构单位电容进行设计与建模,完成了单调转换电容阵列的设计,从而有效地改善了模数转换器的速度与功耗;同时在传统动态比较器的顶端采用MOS管恒流源从而有效地提高了比较器的线性度,并对比较器的分辨率和传输延时进行了仿真;最后设计完成了异步控制电路从而实现了异步控制时序,有效地提高了模数转换器的速度和功耗利用率。通过Cadence设计平台完成了整体电路版图的设计并进行了前后仿,前仿实验结果表明,在1.8V电源电压下,所设计的逐次逼近模数转换器的采样率为120MS/s,当输入信号频率为1.3MHz时,SNR为36.9dB,SNDR为35.8dB,SFDR为48.4dB,ENOB为5.66bit,功耗为2.43mW,FOM值为0.41pJ/Con.step。
[Abstract]:The rapid development of wearable mobile devices, infrared sensors and wireless sensor networks has put forward higher requirements for the miniaturization of electronic systems, and the analog-to-digital converter is an essential part of the system. Its performance directly affects the performance of the whole system, and successive approximation A / D converter has been widely used for a long time because of its low power consumption, small area, moderate speed and so on. Therefore, the design technology has been paid more and more attention. Firstly, this paper analyzes the common structure and working principle of ADC, and compares their advantages and disadvantages. At the same time, the capacitive arrays in successive approximation A / D converters are analyzed and compared from the angle of dynamic power consumption and nonlinear parameter INL/DNL. On this basis, a 6-bit 120MS / s successive approximation analog-to-digital converter circuit is designed. The unit capacitance of sandwich / insert hybrid structure is designed and modeled. The design of monotone conversion capacitor array is completed, which can effectively improve the speed and power consumption of A / D converter. At the same time, the MOS tube constant current source is used at the top of the traditional dynamic comparator to improve the linearity of the comparator effectively, and the resolution and transmission delay of the comparator are simulated. Finally, the asynchronous control circuit is designed to realize the asynchronous control sequence. The efficiency of speed and power efficiency of the ADC is improved effectively. The layout of the whole circuit is designed by using Cadence design platform, and the antecedent simulation results show that. At 1.8V supply voltage, the sampling rate of the successive approximation A / D converter is 120 Ms / s, and the SNR is 36.9 dB when the input signal frequency is 1.3 MHz. The SNDR is 35.8dBnSFDR (48.4dBN) and the power consumption is 2.43mWN (0.41 pJ / Con.Step.)
【学位授予单位】：南京邮电大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792

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