基于180nm CMOS工艺的SAR ADC优化设计研究

发布时间：2018-01-06 02:27

本文关键词：基于180nm CMOS工艺的SAR ADC优化设计研究　出处：《中国科学技术大学》2017年硕士论文　论文类型：学位论文

【摘要】：在粒子物理实验中,探测器首先将粒子携带的物理信息转化为电信号,再由读出电子学系统处理,测量信号的时间、电荷等信息。其中电荷测量占有重要地位,其测量结果对应粒子与探测器相互作用过程中的能量损失,因而对测量能谱、识别成分等有重要作用。成形放大结合数字寻峰方法是电荷测量中的一种常用技术,可以实现高测量精度和线性,因此得到广泛的研究和使用。此方案中输入信号经放大、成形后通过模拟-数字变换器(Analog-to-Digital Converter,ADC)进行数字化,再配合数字寻峰逻辑实现电荷测量。ADC电路是其中的核心组成部分,其性能指标直接影响整个系统的测量精度。在大型物理试验中,其海量的通道数对电子学设计提出了高集成度、低功耗的要求,因此基于专用集成电路(Application Specific Integrated Circuit,ASIC)技术进行电路集成有重要意义。因为逐次逼进型ADC(Successive Approximation Register ADC,SAR ADC)有低功耗的优点,且可以经过优化设计满足采样率和分辨率的需求,所以成为了物理实验读出电子学研究的一个热点。本论文研究工作集中在SARADC的优化设计上,实际结合国家重大基础设施中关键探测器读出需求,进行了 ASIC的设计和测试。其应用背景为大型高海拔空气簇射观测站(Large High Altitude Air Shower Observatory,LHAASO)中的水切仑科夫辐射探测器阵列(Water Cherenkov Detector Array,WCDA),在总面积约8万平方米的范围内,电子学系统需要对3120个光电倍增管(Photo-Multiplier Tube,PMT)进行大动态范围(1~4000光电子)高精度时间和电荷测量。针对此应用需求,本论文工作中基于180 nm CMOS工艺研究了ADC ASIC的优化设计方法,着重于其性能的优化与提升。文章组织结构如下:第一章先介绍了电荷测量方法,然后介绍了 LHAASO WCDA的研究背景及其电子学整体设计、指标要求,最后明确了此应用对于ADC ASIC的性能要求。第二章介绍了 ADC基本概念、一些有代表性的ADC结构的工作过程和性能特点以及性能指标,并且调研了粒子物理实验中使用的ADC ASIC。这为本论文的优化设计工作提供了参考。第三章介绍了 SAR ADC优化设计方案。首先根据设计指标分析了 SAR ADC性能提升的瓶颈,阐述了影响ADC性能的最主要因素即ASIC中电容型数模转换器(Digital-to-Analog Converter,DAC)的非线性,来源于电容失配。然后对电容失配问题进行了调研分析,并提出了优化设计方案。第四章介绍了验证ASIC电路设计。详细陈述了 SAR ADC的关键电路模块以及多方案下多通道电路的设计方案。第五章介绍了验证ASIC的系统测试结果。基于IEEE的ADC测试标准建立了测试系统并进行了一系列测试。结果表明,通过电路的优化设计,在基带上限输入信号频率下信号噪声失真比(Signal to Noise and Distortion Ratio,SINAD)指标提升了约4 dB;采样率31.25 Msps工作条件下,输入信号频率在整个基带范围内时,有效位都好于9 bits。最后一章中总结了论文工作,并展望了下一步工作规划。
[Abstract]:In particle physics experiment, the detector first physical particles carrying information into electrical signals by the readout electronics system, measurement time, charge and other information. The charge measurement occupies an important position, the energy loss of the measurement results of the interaction process and corresponding particle detector, so the measurement of energy spectrum recognition composition is important. The peak search method based on digital shaping amplifier is a commonly used technique in the charge measurement, can achieve high measurement accuracy and linearity, so has been widely studied and used. In the scheme, the input signal is amplified, formed by an analog to digital converter (Analog-to-Digital Converter, ADC) were digitized with digital peak charge measurement of.ADC logic circuit is one of the core components, its performance directly affects the precision of the whole system in the large. The physical test, the number of channels for its massive electronics design was proposed for high integration, low power requirements, therefore based on ASIC (Application Specific Integrated Circuit, ASIC) has important significance for the integrate circuit technology. Because successive type ADC (Successive Approximation Register on ADC, SAR ADC) has the advantages of low power consumption. And can be optimized to meet the sampling rate and resolution of the demand, so become a hot research read physical experiment. This thesis focused on the optimization design of SARADC, combined with the actual reading demand in key national key infrastructure in the detector, the design and test of ASIC. The application background of large scale high an air shower Observatory (Large High Altitude Air Shower Observatory, LHAASO) in the water Cerenkov radiation detector array (Water Cherenk Ov Detector Array, WCDA), in the range of the total area of about 80 thousand square meters, the electronics system for 3120 photomultiplier tubes (Photo-Multiplier, Tube, PMT) of high dynamic range (1~4000 photoelectron) high precision time and charge measurement. According to the application demand, optimization design method of 180 nm CMOS process is studied based on ADC the work of the ASIC theory, focus on optimizing and improving its performance. The following article structure: the first chapter introduces the charge measurement method, and then introduces the research background of LHAASO WCDA and its electronics overall design requirements, and finally clear this application on the performance of ADC ASIC. The second chapter introduces the ADC the basic concept, some ADC structure representative of the work process and the performance characteristics and performance index, and research the use of particle physics experiments in the ADC ASIC. for the optimization design of Engineering For reference. The third chapter introduces the SAR ADC optimization. Firstly, the bottleneck of SAR ADC performance analysis according to the design index, expounds the main factors affecting the performance of ADC is capacitive ASIC DAC (Digital-to-Analog Converter, DAC) derived from the nonlinear capacitor mismatch. Then the research analysis of capacitor mismatch problems, and puts forward the optimized design scheme. The fourth chapter introduces the verification of ASIC circuit design. A detailed statement of the design of multi-channel circuit key circuit module of SAR ADC and multi scheme. The fifth chapter introduces the system test results verify ASIC. ADC test based on the standard IEEE testing system has been established. And conducted a series of tests. The results showed that by optimizing the circuit design, the upper limit frequency of the input signal in the baseband signal to noise and distortion ratio (Signal to Noise and Distortion Ratio, S INAD) the index has increased by about 4 dB, and the sampling rate is 31.25 Msps. When the input signal frequency is in the whole baseband range, the effective bits are all better than 9 bits.. The last chapter summarizes the work of the paper, and looks forward to the next step work plan.

【学位授予单位】：中国科学技术大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN792

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