温度冲击载荷下POP堆叠封装可靠性研究

发布时间：2018-01-06 08:44

本文关键词：温度冲击载荷下POP堆叠封装可靠性研究　出处：《江苏大学》2015年硕士论文　论文类型：学位论文

【摘要】：随着电子科学和封装技术的飞速发展,电子产品的升级和更换更加频繁。消费者对电子科技类产品的性能需求日益提高,迫使电子封装密度不断增大。近年以来电子封装技术不断向小尺寸、高密度、高性能等方向发展。封装方式也逐渐由二维封装向空间叠层封装转变。叠层封装POP技术被认为是未来相当长时间内电子封装技术的主要发展方向。它是将逻辑运算器件和存储器件集成在同一封装体内,不仅在封装体积没有增加的情况下提高了封装密度,而且减小了由封装线路所带来的RC延迟。但是由于封装密度的提高,电子产品在使用过程中热量更加容易堆积,会对电子产品的可靠性产生严重的影响。本文便针对POP堆叠封装芯片在温度冲击载荷下的可靠性进行了实验和模拟方面的研究。本文的主要工作如下：本文针对POP堆叠封装结构,对其进行了温度冲击载荷下的可靠性模拟,得到了POP堆叠封装应力应变的分布特点及其随时间变化规律。基于理论计算结果预测了焊点的寿命。本文选用了Amkor公司的14mm×14mm的POP封装芯片作为模拟研究的对象。由于模拟对象为中心对称结构,本文构建了POP堆叠芯片的1/4模型并对其进行了合理的简化,并根据JEDEC的加载标准对其进行了温度冲击载荷下的模拟研究。结果表明：在温度冲击载荷下整个封装体的应力主要集中在芯片和焊球上,而整个封装体的最大应力出现在底层焊球的角端上底层焊球的应力大小呈现出由中心到边缘逐渐增大的趋势,而顶层焊球之间的应力大小无明显的变化趋势。本文采用了Kencht-Fox焊点寿命预测模型,理论上计算了焊点的疲劳寿命。本文根据样品在温度冲击载荷下的应变测试原理,搭建了实验测试平台。实验测试了在温度冲击载荷下POP堆叠封装焊点的应变情况。选取了Amkor公司的14mm×14mm与15mm×15mm的两片封装体积不同POP堆叠芯片作为实验对象。对两个POP堆叠组件的上下两层封装焊点在温度载荷下的应变分别进行了记录与分析。实验结果表明：POP堆叠封装的底层焊点的应变幅要大于顶层焊点的应变幅。在相同温度载荷下底层封装焊点的热可靠性要低于顶层封装焊点。计算了实验条件下的焊点寿命并将实验计算结果与模拟计算结果进行了对比,误差约为20%,证明其结果具有一定的相似性。对比研究了两块封装体积不同的封装芯片,结果表明15mm×15mm的封装芯片其上下层焊点的应变幅分别大于14mm×14mm上下层焊点的应变幅。经计算发现在相同温度载荷下15mm×15mm封装芯片的可靠性低于14mm×14mm封装芯片的可靠性。表明在相同温度冲击载荷下,芯片封装体积对于焊点的可靠性具有一定的影响,封装体积越大,焊点可靠性越低。综上所述,本文针对POP封装的可靠性进行了实验与模拟研究,对比分析了在同一温度冲击载荷下的模拟与实验的结果,证明理论模拟的准确性,探寻可以使用数值模拟的办法替代实验测试的可行性。对比分析了在相同温度载荷下不同封装体积的POP堆叠芯片的可靠性的情况。其结论可以为三维封装的可靠性研究提供一定的理论参考,对POP封装测试和优化设计也具有一定的指导和借鉴意义。
[Abstract]:With the rapid development of Electronic Science and technology of electronic packaging, product upgrades and replacement of more frequent. Consumer demand on the performance of electronic technology products increasing, forcing the electronic packaging density increasing. In recent years, electronic packaging technology to small size, high density, high performance and so on. The package mode is gradually change from 2D package to space laminated package. POP package technology stack is considered to be the main development direction in the future for quite a long time in the electronic packaging technology. It is the logical device and the memory device is integrated in the same package, not only in the packaging volume did not increase under the condition of increasing packaging density, but also reduce the brought the packaging line RC delay. But due to the increase of the density of electronic product packaging, heat in the process of using easy accumulation, will have on the reliability of electronic products Seriously affected. This paper is directed to the POP chip stack package reliability in temperature under impact load are studied by experimental and simulation. The main work of this paper is as follows: This paper POP stack package structure to simulate the reliability of temperature under impact load, POP stacked package stress distribution and strain with time changes to the theoretical calculation results. The solder joint life. Based on the object of this paper uses POP's Amkor chip package 14mm * 14mm as simulation study. Because the simulated object centered symmetrical structure, this paper constructs a 1/4 model of POP chip and the stack is simplified reasonably, and according to the the loading of the JEDEC standard has carried on the simulation of temperature under impact load. The results showed that the temperature stress under impact load the whole package mainly focused on chip and welding The ball, and the whole package of the maximum stress appears in the bottom corner of the solder ball on the bottom of the solder ball stress size increased from the center to the edge of the trend, and between the top solder ball stresses have no obvious trend. This paper adopts Kencht-Fox solder joint life prediction model theory to calculate the fatigue life of solder joints. Based on the principle of strain testing samples at temperatures under impact load, built a test platform. The experimental strain POP stacked package solder joints under temperature shock loads. Selected two pieces of different package size POP stacked chip of Amkor company 14mm * 14mm and 15mm * 15mm as the experimental object. The strain two POP stack assembly down two package solder joints under temperature load were recorded and analyzed. The experimental results show that the bottom of the stacked package solder joints of POP strain To be greater than the top spot in the same strain. Under temperature load thermal reliability of solder joints is lower than the bottom of the top package solder joints under the experimental conditions. The calculated and experimental results of fatigue life and the simulation results were compared, the error is about 20%. The results show that a certain similarity. A comparative study of the package two different chip package volume. The results show that the packaged chip 15mm * 15mm of the upper and lower joint strain were more than 14mm * 14mm on the lower joint strain. Found by calculating the reliability at the same temperature under the load of 15mm * 15mm * 14mm chip is lower than that of 14mm chip. In the same temperature shock under load, the chip package volume has certain effect on the reliability of solder joints, the package volume is large, the lower the reliability of solder joints. In summary, this paper aiming at the reliability of POP package The experimental research and simulation, comparative analysis at the same temperature shock loading simulation and experimental results, to prove the accuracy of theoretical simulation, to explore the feasibility of numerical simulation can be used to replace the test. Comparative analysis of the reliability at the same temperature under load with POP stacked chip package size case. The conclusions can provide some theoretical reference for the study on the reliability of the 3D packaging, also has certain guidance and reference for the POP packaging and testing and optimization design.

【学位授予单位】：江苏大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN05

【共引文献】