FPGA并行时序驱动布局算法

发布时间：2018-01-06 16:29

本文关键词：FPGA并行时序驱动布局算法　出处：《计算机工程》2017年02期 　论文类型：期刊论文

【摘要】：传统的基于模拟退火的现场可编程门阵列(FPGA)时序驱动布局算法在时延代价的计算上存在一定误差,已有的时序优化算法能够改善布局质量,但增加了时耗。针对上述问题,提出一种基于事务内存(TM)的并行FPGA时序布局算法TM_DCP。将退火过程分发至多线程执行,利用TM机制保证共享内存访问的合法性,并将改进的时序优化算法嵌入到事务中并发执行。测试结果表明,与通用布局布线工具相比,8线程下的TM_DCP算法在总线长仅有轻微增加的情况下,关键路径时延平均降低了4.2%,同时获得了1.7倍的加速,且其执行速度随线程数的增加具有较好的可扩展性。
[Abstract]:There is a certain error in the time delay cost calculation of the traditional time sequence driven layout algorithm based on simulated annealing, and the existing timing optimization algorithm can improve the layout quality. In view of the above problems, a parallel FPGA timing layout algorithm based on transaction memory (TMTM) is proposed, which distributes the annealing process to multi-thread execution. The TM mechanism is used to guarantee the legitimacy of shared memory access, and the improved timing optimization algorithm is embedded into the transaction to execute concurrently. The test results show that the algorithm is compared with the general layout and routing tool. The TM_DCP algorithm under 8 threads can reduce the critical path delay by 4.2 times and obtain 1.7 times acceleration when the bus length is only slightly increased. And its execution speed increases with the number of threads has a better scalability.
【作者单位】：国家数字交换系统工程技术研究中心;
【基金】：国家“863”计划重大项目(2014AA01A704) 国家自然科学基金(61572520)
【分类号】：TN791
【正文快照】： 中文引用格式:张家齐,沈剑良,朱珂.FPGA并行时序驱动布局算法[J].计算机工程,2017,43(2):98-104.英文引用格式:Zhang Jiaqi,Shen Jianliang,Zhu Ke.Parallel Timing-driven Placement Algorithm for FPGA[J].Computer Engineering,2017,43(2):98-104.0概述现场可编程门阵列(Fi

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