45nm芯片铜互连结构低k介质层热应力分析

发布时间：2018-01-06 16:25

本文关键词：45nm芯片铜互连结构低k介质层热应力分析　出处：《半导体技术》2017年01期 　论文类型：期刊论文

【摘要】：采用铜互连工艺的先进芯片在封装过程中,铜互连结构中比较脆弱的低介电常数(k)介质层,容易因受到较高的热机械应力而发生失效破坏,出现芯片封装交互作用(CPI)影响问题。采用有限元子模型的方法,整体模型中引入等效层简化微小结构,对45 nm工艺芯片进行三维热应力分析。用该方法研究了芯片在倒装回流焊过程中,聚酰亚胺(PI)开口、铜柱直径、焊料高度和Ni层厚度对芯片Cu/低k互连结构低k介质层应力的影响。分析结果显示,互连结构中间层中低k介质受到的应力较大,易出现失效,与报道的实验结果一致;上述四个因素对芯片低k介质中应力影响程度的排序为:焊料高度PI开口铜柱直径Ni层厚度。
[Abstract]:In the packaging process of advanced chips using copper interconnection technology, the weak low dielectric constant (K) dielectric layer in copper interconnection structure is vulnerable to failure due to higher thermal mechanical stress. The problem of chip encapsulation interaction (CPI) is presented. Using the finite element submodel, the equivalent layer is introduced into the whole model to simplify the micro structure. Three-dimensional thermal stress analysis of 45nm process chip was carried out. The polyimide (Pi) opening and the diameter of copper column were studied during reverse reflux welding. The effect of solder height and Ni layer thickness on the low-k dielectric layer stress of the Cu-low k interconnect structure is analyzed. The results show that the stress in the intermediate layer of the interconnect structure is large and it is prone to failure. The experimental results are consistent with the reported results. The order of influence of the above four factors on the stress in low k medium is as follows: solder height Pi open copper column diameter Ni layer thickness.
【作者单位】：复旦大学材料系;华进半导体封装先导技术研发中心有限公司;
【基金】：国家科技重大专项资助项目(2014ZX02501)
【分类号】：TN405.97
【正文快照】： 2.华进半导体封装先导技术研发中心有限公司,江苏无锡,214135)0引言随着特大规模集成电路(ultra large scale inte-gration,ULSI)的不断发展,互连引线的宽度越来越小,出现了显著的RC延迟问题[1]。为了降低RC延迟,在互连结构中采用铜和低介电常数(k)材料,分别代替铝和Si O2作为

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