基于FPGA数字集成电路的可测性实现

发布时间：2018-01-08 09:03

本文关键词：基于FPGA数字集成电路的可测性实现　出处：《黑龙江大学》2015年硕士论文　论文类型：学位论文

【摘要】：如今,集成电路产业飞速发展,IC产品变得功能多、速度快、功耗低、封装微型化的同时,问题也随之而来:第一,IC功能增多,一个芯片往往集成了数百万至数千万不止的元器件,引脚数目增多,集成度增高;第二,封装技术复杂化、微型化致使每个单元之间的连线越加狭窄,引脚间越加细密。这些无疑都增加了IC测试的时间、功耗与难度,降低了芯片物理访问性。传统基于物理接触的测试技术根本无法跟上IC发展的步调,IC测试遭遇瓶颈。在此背景下,可测性设计方法被提出,并以其简捷、自动化的特点高效的克服了上述问题,被迅速推广应用于各个领域。本文的主要工作是采用IEEE1149.1标准实现针对数字电路的边界扫描自测试结构的设计。通过一个16位状态机的边界扫描控制器协调控制各个测试存取通道和各类寄存器模块,实现测试向量的加载、移位、更新、测试响应的捕获。最后将测试控制电路、被测电路、测试分析电路整体下载至开发板,实施对电路故障的诊断,达到自测试的目的。设计中采用LFSR生成一系列二进制伪随机数作为测试生成向量,用于有效测试向量的提取。本文在QuartusII设计软件环境下,采用Verilog编写实现边界扫描测试各部分电路的功能,最终由FPGA进行整体设计的实现。
[Abstract]:Nowadays, with the rapid development of IC industry, IC products have become more functional, faster, lower power consumption, and packaging miniaturization. At the same time, problems have followed: first, the number of IC functions has increased. A chip often integrates millions to tens of millions of components, the number of pins increased, the integration level increased; Second, the packaging technology is complicated, miniaturization causes each unit to be more narrow in connection, and the pin is more and more detailed, which undoubtedly increases the time, power consumption and difficulty of IC test. The traditional testing technology based on physical contact can not keep up with the development of IC to meet the bottleneck of IC testing. In this context, the testability design method is proposed, and its simplicity. The characteristics of automation effectively overcome the above problems. The main work of this paper is to implement the design of boundary scan self-test structure for digital circuits by using IEEE1149.1 standard. The boundary of a 16-bit state machine is adopted. The scan controller coordinates and controls each test access channel and various register modules. Finally, the test control circuit, the tested circuit, the test analysis circuit is downloaded to the development board, and the fault diagnosis of the circuit is implemented. In the design, a series of binary pseudorandom numbers are generated by LFSR as test generation vectors. In this paper, under the environment of QuartusII design software, we use Verilog to realize the function of boundary scan test circuit. Finally, the overall design is implemented by FPGA.
【学位授予单位】：黑龙江大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN407;TN791

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