基于DDS和PLL的低相噪频率合成器的优化设计

发布时间：2018-01-09 03:31

本文关键词：基于DDS和PLL的低相噪频率合成器的优化设计　出处：《华中科技大学》2015年硕士论文　论文类型：学位论文

【摘要】：随着现代社会计算机技术的不断发展,网络通信的工作量日益增大,这对现代通信系统而言是一个巨大的挑战,大量的信息传递和通道的并行对通信设备提出了很高的要求。物联网、雷达和测试仪器等各方面的发展都需要一个性能优异的频率合成器提供信号源,对频率源的频带范围、相噪和杂散表现、频率稳定度以及跳频时间都提出了更高的要求。信息化时代带动通信产业的不断发展,频率源作为电子通信系统中的关键模块,拥有着巨大的市场需求和广阔的发展前景。这也促使工程师们对其性能进行不断地提升和完善。本文首先介绍了频率合成技术的相关理念、实现方式以及锁相式频率合成技术的国内外发展情况和研究背景。简单阐述了锁相环结构的基本理论,并分析了其相位噪声和杂散特性。之后,基于现有的DDS模块研究讨论了多种DDS+PLL的优化方案,包括DDS与PLL环外混频、DDS与PLL环内混频、DDS直驱PLL和DDS直驱结合内插的结构,并确定了初步的技术方案,针对此结构滤波困难的问题,相应设计了一个预锁定结构来辅助锁定,改变主环反馈频率便于滤波处理。在兼顾成本和系统复杂度的基础上,最终确立了采用具备双环结构的DDS与PLL环内混频方案。根据确立的方案进行合理的器件选型、仿真设计,参考芯片的数据手册搭建了完整的电路原理图,完成了PCB版图的绘制,并逐步焊接与完成了系统的制作。最后的测试表明,所制作的频率源具有优异的相位噪声表现,在10kHz频偏处的相位噪声优于-115dBc/Hz,杂散抑制优于-67dBc,后续针对系统输出频率范围和锁定时间的不足提出了改进建议。
[Abstract]:With the development of computer technology in modern society, the workload of network communication is increasing day by day, which is a great challenge to modern communication system. A large number of information transfer and channel parallel to the communication equipment put forward very high requirements. The development of Internet of things radar and testing instruments and other aspects of the development need a frequency synthesizer with excellent performance to provide a signal source. Higher requirements for frequency range, phase noise and spurious performance, frequency stability and frequency hopping time are put forward. The information age drives the continuous development of the communication industry. Frequency source is a key module in electronic communication system. There is a huge market demand and broad development prospects. This also urges engineers to continuously improve and improve their performance. Firstly, this paper introduces the related concepts of frequency synthesis technology. The development and research background of phase-locked frequency synthesis technology at home and abroad. The basic theory of PLL structure and its phase noise and spurious characteristics are briefly expounded. Then the phase noise and spurious characteristics of PLL structure are analyzed. Based on the existing DDS modules, several optimization schemes of DDS PLL are discussed, including DDS and PLL outer mixing DDS and PLL internal mixing. DDS direct drive PLL and DDS direct drive combined with interpolation structure, and determined the preliminary technical scheme, aiming at this structure filter difficult problem, corresponding design a pre-lock structure to assist locking. Changing the feedback frequency of the main loop is convenient for filtering and processing. On the basis of considering the cost and the complexity of the system. Finally, the scheme of internal mixing of DDS and PLL with double loop structure is established. According to the established scheme, reasonable device selection and simulation design are carried out. Reference to the data manual of the chip to build a complete circuit schematic, completed the PCB layout drawing, and gradually welding and completion of the system. Finally, the test shows. The frequency source has excellent phase noise performance, the phase noise at 10kHz frequency offset is better than -115dBc / Hzand the spurious suppression is better than -67dBc. Suggestions for improvement of system output frequency range and locking time are put forward.
【学位授予单位】：华中科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN74

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