基于单速率滤波器组技术的高效数字信道化接收算法研究及FPGA实现

发布时间：2018-01-10 21:38

本文关键词：基于单速率滤波器组技术的高效数字信道化接收算法研究及FPGA实现　出处：《东南大学》2015年硕士论文　论文类型：学位论文

【摘要】：数字信道化接收机具有瞬时带宽大、动态范围大、频率选择性能好等诸多优点,在现代电子战中具有重要作用。针对以多相滤波器组为核心的数字信道化技术复杂度高、相邻通道的可拼接性较差等问题,本文研究基于单速率滤波器组技术的数字信道化算法及FPGA实现。论文的主要工作包括：研究了用于实现数字信道化结构的单速率滤波器组算法及其相关算法,基于PXIe模块化虚拟仪器,在Labview FPGA平台上实现了数字信道化接收机核心模块及其外围功能模块,并完成了人机交互界面设计及性能测试。首先,介绍了数字信道化技术研究的背景及意义,并通过分析国内外研究现状,认识到国内对数字信道化技术的研究还很不足,由此得出研究数字信道化技术的算法及实现是十分有必要的。然后,介绍了数字信道化接收机的整体架构,分析了比较常用的信道化结构即基于FFT的信道化结构的原理和缺陷,以及可以弥补FFT滤波性能欠缺的可能途径。其一,基于多相滤波器组的信道化方法可以克服FFT滤波器阶数与点数之间固定关系的限制,但是需要较多的乘法器资源。其二,基于快速滤波器组(FFB)的信道化方法,不但能弥补FFT原型子滤波器滤波性能不佳的缺陷,设计高性能的滤波器组参数；而且基于频罩法设计子滤波器系数,与FFT比较复杂度基本相当。本节首先研究了FFB算法的推导、基于频罩法的子滤波器系数的设计和基于节点调制的FFB改进算法。其次比较了FFT,多相滤波器组和FFB在滤波性能、乘法器消耗量和应用场景等方面的性能。最后进一步研究了诸如子信道抽取算法和子信道有效数据检测算法的信道化后续处理算法。接着,本节在PXIe模块化仪器上基于Labview FPGA平台设计并实现了50MHz分析带宽、64通道数字信道化接收机。首先阐述了系统各个模块的设计思想,然后详细描述了各个模块的实现过程。系统模块包括数字信道化核心模块、数字信道化后续处理模块、高速数据传输模块、射频信号流盘模块和射频信号回放模块。数字信道化核心模块是整个系统的核心,实现源采样信号的信道化滤波：数字信道化后续处理模块包括子信道的下采样模块和信道检测模块,实现子信道的有效数据检测和降速处理；高速数据传输模块实现FPGA与主控器之间的高速信息交互与可靠实时传输；射频信号流盘模块和射频信号回放模块用来进行源采样数据的录制和多次回放分析。最后,介绍了整个系统的硬件仪器的搭建包括矢量信号分析仪的搭建和矢量信号发生器的搭建,并在Labview FPGA平台上对整个数字信道化接收机系统进行了性能测试,将测试结果与理论结果进行分析对比,验证了系统的正确性。
[Abstract]:Digital channelized receiver has many advantages, such as large instantaneous bandwidth, large dynamic range and good frequency selection performance. It plays an important role in modern electronic warfare. The digital channelization technology with polyphase filter banks as the core has high complexity and poor splicing ability of adjacent channels. In this paper, the digital channelization algorithm based on single-rate filter banks and its FPGA implementation are studied. The main work of this thesis is as follows:. A single rate filter bank algorithm and its related algorithms for digital channelization are studied. Based on PXIe modular virtual instrument, the core module of digital channelized receiver and its peripheral function module are realized on Labview FPGA platform. The human-computer interface design and performance test are completed. Firstly, the background and significance of digital channelization research are introduced, and the current research situation at home and abroad is analyzed. It is very necessary to study the algorithm and implementation of digital channelization technology. Then, the whole architecture of digital channelization receiver is introduced. This paper analyzes the principle and defects of the channelized structure based on FFT, and the possible ways to make up for the lack of FFT filtering performance. The channelization method based on polyphase filter banks can overcome the limitation of the fixed relationship between the order and the number of FFT filters, but it needs more multiplier resources. The channelization method based on fast filter banks can not only make up for the poor filtering performance of FFT prototype sub-filters, but also design high performance filter bank parameters. Moreover, the design of subfilter coefficients based on the frequency mask method is similar to that of FFT. In this section, the derivation of FFB algorithm is first studied. The design of subfilter coefficients based on frequency mask method and the improved FFB algorithm based on node modulation. Secondly, the filtering performance of FFT, polyphase filter banks and FFB are compared. The performance of multiplier consumption and application scenarios. Finally, the channelized follow-up processing algorithms such as subchannel extraction algorithm and subchannel effective data detection algorithm are further studied. In this section, 50MHz analysis bandwidth is designed and implemented on PXIe modular instrument based on Labview FPGA platform. Firstly, the design idea of each module of the system is introduced, and then the realization process of each module is described in detail. The system module includes the core module of digital channelization. Digital channelization follow-up processing module, high-speed data transmission module, radio frequency signal streaming disk module and radio frequency signal playback module. Digital channelization core module is the core of the whole system. To realize channelization filtering of source sampling signal: digital channelization follow-up processing module includes subchannel downsampling module and channel detection module to realize effective data detection and speed reduction of subchannel; The high-speed data transmission module realizes the high-speed information exchange and reliable real-time transmission between the FPGA and the main controller. The radio frequency signal stream disc module and the radio frequency signal playback module are used to record the source sampling data and analyze the multiple playback data. Finally. The hardware structure of the whole system includes the construction of the vector signal analyzer and the construction of the vector signal generator. The performance of the whole digital channelized receiver system is tested on the Labview FPGA platform. The correctness of the system is verified by comparing the test results with the theoretical results.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN713;TN971;TN851

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