FT-SerDes CDR关键电路设计

发布时间：2018-01-11 09:20

本文关键词：FT-SerDes CDR关键电路设计　出处：《国防科学技术大学》2015年硕士论文　论文类型：学位论文

【摘要】：串行/解串器(Serializer/Deserializer,缩写SerDes)是数据传输中的收发机功能模块。互联芯片间传输串行数据时,是通过SerDes在每个方向上转换串行数据与并行端口之间的传输,反之亦然。它通常应用在高速数据通信系统中,弥补有限的输入/输出端口数,在差分线上传输数据,提高了数据抗干扰能力,减少I/O引脚和互联线。SerDes互联技术是当今主流的数据传输方式。本文设计了两倍过采样,数据对齐与数据解串,采样时钟的相位检测,二阶数字滤波器,数据编码,以及DAC与PI电路模块。具体研究工作包括以下几个方面:1、使用两倍过采样方式设计采样电路,实现对差分数据的过采样,使采样数据包含时钟信息。对每连续的两个数据位捕获四个采样值,两个边沿信息和两个数据信息,用来恢复同步时钟。为了把差分数据转换为单端数据,增加了一个双端数据到单端转换的电路,采用特殊的Latch电路结构。为了克服对数据的亚稳态采样,增加了二级采样模块。使用Hspice仿真验证过采样电路功能,利用Spectre仿真验证二级采样结构能克服亚稳态采样。2、为实现对采样数据的并行处理,设计专用的数据对齐(Alignment)与数据解串器(Deserializer)电路。通过数据对齐电路,对采样得到的两类数据,即数据信息和数据边沿信息,分别进行数据对齐。数据对齐后经过两级特殊的DEMUX电路,即DEMUX 2:4与DEMUX 1:5,数据信息与数据边沿信息分别转换为并行的20位数据。使用Hspice仿真验证了数据对齐与DEMUX电路,数据速率在2.5Gbps下可以正确解串。并通过了NC-Verilog对FT-Ser Des系统的混合仿真。3、通过设计相位检测二阶数字滤波器,利用采样数据中包含的时钟信息,提取同步时钟。建立二阶数字滤波器的数学模型,并使用Matlab验证模型性能,使其满足Jury criteria[1][2]稳定三角形,实现二阶数字滤波器在阶跃响应下稳定。在电路设计实现上,使用Bang-Bang[3][4]算法检测时钟的相位,判断采样时钟的相位是超前还是滞后于数据中心点的位置。通过Vote Majority(多数投票机)比较相位检测的结果。使用FSM(状态机)对Vote Majority的输出进行积分处理(循环加减),得到采样时钟相位与理想时钟相位的量化误差。通过NC-Verilog混合仿真验证,实现了时钟相位的跟踪,正确接收到了数据。4、采用数据编码电路,实现对二阶数字滤波器输出量的转换,控制DAC与PI(Phase Interpolation)[5][6][7]。通过设计专用的编码电路,把10bit量化误差转换为3组共27对差分数字控制信号。控制DAC的精度和参与插值的8相时钟的选择,选择相邻的两相时钟进行插值。使用Spectre仿真验证了编码电路的功能。5、在调整采样时钟的相位与数据中心点的位置中,通过使用DAC控制PI电路,实现时钟相位的前后调节。设计以电流源控制的专用DAC电路,转换精度为4bit,分辨率为LSB?1/16。INL(积分非线性)与DNL(差分非线性)的值分别为,-3LSB?INL?2LSB,-0.5LSB?DNL?0.5LSB,满足DAC转换的单调线性。设计PI电路,对选择的两个时钟进行相位插值,得到的时钟是两个时钟的加权和,即输出时钟的相位在两个输入时钟的相位之间。相位插值的动态范围覆盖整个时钟周期。参与插值时钟的权值系数a,b,满足a?b?1,相位调节的精度约等于2.8°。使用AMS混合仿真器,对DAC与PI整体验证仿真,实现了插值时钟相位变化的单调线性。
[Abstract]:Serializer / deserializer (Serializer/Deserializer, abbreviated SerDes) is a transceiver function module data transmission in Internet. Inter chip serial data transmission, transmission, conversion between the SerDes serial data in each direction and parallel port and vice versa. It is usually used in high speed data communication system, to make up for the limited input / output the number of ports, data transmission in differential line, improve the anti-interference ability of data, reduce the I/O pin and the interconnection of.SerDes interconnect technology is the mainstream of today's data transmission. This paper designed two times of sampling, data alignment and data string, phase detection of sampling clock, two order digital filter, data encoding. And the DAC and PI circuit module. The specific work includes the following aspects: 1, use two times of sampling design of sampling circuit, sampling differential data, the sampling data packet Containing the clock information. For each of two consecutive bits of data capture four samples, two edge information and two data information, to restore the synchronized clock. In order to put the differential data into single ended data, added a double end data to the single ended conversion circuit, Latch circuit with special structure. In order to overcome the sampling of metastable data, an increase of two level sampling module. Using Hspice simulation sampling circuit function verification two sampling structures can overcome metastable.2 sampling using Spectre simulation, in order to realize the parallel processing of sampling data, a data alignment meter special (Alignment) and data deserializer (Deserializer) circuit. By aligning circuit data of two kinds of data sampling, data information and data edge information is used in data alignment. Data alignment after DEMUX circuit two special, namely DEMUX 2:4 And DEMUX 1:5, data information and data edge information were converted to 20 bit parallel data. Using Hspice simulation data is aligned with the DEMUX circuit, the data rate can be correctly deserialized in 2.5Gbps. And through the.3 NC-Verilog of FT-Ser Des hybrid simulation system, through the design of phase detection of two order digital filter, using the clock information in the sample data, extract the synchronous clock. Mathematical model of two order digital filter, and use Matlab to verify the performance of the model, which can meet the Jury criteria[1][2] stable triangle, the realization of the two order digital filter in step response stability. In circuit design, using Bang-Bang[3][4] algorithm to detect the phase of the clock, the judgment phase sampling clock is ahead or behind the data center position. By Vote Majority (majority voting machine) the phase detection using FSM (state machine). The output of the Vote Majority integral process (cyclic addition and subtraction), get the quantization error of sampling clock phase and the ideal clock phase. Through NC-Verilog hybrid simulation, the clock phase tracking, correctly received data using.4, data encoding circuit, realize the conversion of the output of the two order digital filter volume control, DAC with PI (Phase Interpolation [5][6][7].) through the encoding circuit design for 10bit, the quantization error is converted into 3 groups of 27 pairs of differential digital control signals. The accuracy of DAC control and participate in the interpolation of the 8 phase clock selection, selection of two adjacent clock interpolation. Using Spectre simulation to verify the function of.5 encoding circuit. In phase with the data center to adjust the position of the sampling clock, through the use of DAC PI control circuit, realize the clock phase adjustment. The special DAC circuit design on current source control, Conversion accuracy is 4bit, the resolution is LSB? 1/16.INL (integral nonlinear) and DNL (differential nonlinearity) values for -3LSB, 2LSB, INL respectively?? -0.5LSB? DNL? 0.5LSB and DAC meet the monotone linear transformation. PI circuit design, phase interpolation of two clock selection, the clock is weighted and two of the clock, the phase of the output clock phase between the two input clock. The dynamic range of phase interpolation covering the entire clock cycle. The weight coefficient in interpolation a clock B, meet a? B? 1, phase adjustment accuracy is approximately equal to 2.8 degrees. The use of DAC and AMS hybrid simulator PI overall verification simulation, realized the monotone linear interpolation clock phase change.

【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402

【相似文献】