用于高速插值ADC设计的量化模型研究

发布时间：2018-01-12 11:11

本文关键词：用于高速插值ADC设计的量化模型研究　出处：《电子科技大学》2015年硕士论文　论文类型：学位论文

【摘要】：高速模数转换器(ADC)被广泛应用于超带宽系统、硬盘驱动读取信道、无线系统、雷达探测系统等领域。而随着电子产品功能的发展,对模数转换器的性能要求越来越高,为了适应这些要求,ADC主要向低功耗、高分辨率和高速度方向发展,同时也增加了高速ADC的设计难度。在高速ADC的设计中,即使对于经验丰富的工程师,也需要大量的重复仿真与优化来尝试不同的结构和设计参数,通过枚举的方法找出一个相对优化的设计方案。然而,这种传统的设计方法既繁琐费时又不够科学严谨,为了解决这一问题,本文将针对高速ADC中预放大器阵列的结构、带宽和失调电压进行深入研究。在现有的高速ADC量化模型和辅助设计方法研究的基础上,本文提出了一种适用于高速ADC的量化模型,并在此基础上提出一种辅助高速ADC设计的方法。该量化模型适用于典型的带插值/均值技术的多级式预放大器阵列,通过一组输出节点静态电流方程表征预放大器阵列的静态工作状态,通过小信号电流方程组表征预放大器阵列的小信号模型,将整个预放大器阵列近似等效为一个单极点系统,同时借助计算机数据拟合和迭代算法,可以计算得出不同设计参数下预放大器阵列的增益和带宽。再结合不同工艺库中器件失配参数和预放大器阵列的小信号模型,可计算出预放大器阵列的失调电压,从而建立起一套适用于高速ADC的预放大器阵列的量化模型,同时也得到一种借助于计算机的高速ADC设计的辅助方法。本文首先简述了高速ADC量化模型的研究动态和理论基础,然后详细剖析了常见高速ADC的设计难点及关键技术,随后对提出的量化模型进行了理论推导,并详细阐述了辅助设计方法的原理、适用范围和验证结果。最后借助Hspice仿真软件,基于TSMC 65nm工艺对验证电路的单个模块和整体系统进行了仿真与验证。结果表明该量化模型和辅助设计方法在实际的高速ADC设计中具有较高的准确性和可行性。
[Abstract]:High speed analog-to-digital converter (ADC) is widely used in ultra wideband system, hard disk drive read channel, wireless systems, radar detection system. With the development of electronic product function, performance requirements of the analog-to-digital converter is more and more high, in order to meet these requirements, ADC mainly to low power consumption, high resolution and high speed development direction at the same time, also increased the difficulty of the design of high speed ADC. In the design of high speed ADC, even for experienced engineers, also need to repeat the simulation and optimization of a large number of attempts to structure and different design parameters, through the enumeration method to find a relatively optimal design. However, this traditional method not only time-consuming and lack of scientific rigor, in order to solve this problem, this paper will focus on the structure of pre amplifier array in high speed ADC, bandwidth and offset voltage is researched. In the existing high speed AD C based quantitative model and aided design method research, this paper presents a quantitative model for high speed ADC, and proposes a method of auxiliary high-speed ADC design. The quantitative model for multi-stage pre amplifier array in typical interpolation / mean technology, through a static state set the output node static current equation pre amplifier array, the small signal model of small signal current equations characterization of pre amplifier array, the preamplifier array equivalent to a single pole system, with the help of computer data fitting and iterative algorithm can calculate the gain and bandwidth of pre amplifier arrays with different design parameters. Combined with the small signal model of the device mismatch parameters and pre amplifier arrays of different process library, can calculate the offset voltage pre amplifier array, in order to establish Quantitative model of pre amplifier array applied to a set of high speed ADC, but also by an auxiliary method of high-speed ADC design with the help of a computer. This paper first introduces the research of high speed ADC quantitative model and dynamic theory, and then a detailed analysis of the design difficulties and key technology of common high-speed ADC, then the quantitative model this paper describes the principle, and design method, the applicable scope and verification results. Finally, using Hspice simulation software, TSMC 65nm technology to verify the circuit of single module and the whole system based on the simulation and verification. The results show that the accuracy and feasibility of the quantitative model and aided design method has high in high speed the practical design of ADC.

【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792

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