四阶前馈低功耗Sigma-Delta调制器设计

发布时间：2018-01-13 05:28

本文关键词：四阶前馈低功耗Sigma-Delta调制器设计　出处：《哈尔滨工业大学》2015年硕士论文　论文类型：学位论文

【摘要】：根据采样频率的不同,模数转换器被分为Nyquist ADC和Sigma-Delta ADC两类。Sigma-Delta ADC由调制器和数字抽取滤波器两部分组成,调制器利用过采样技术和噪声整形技术降低信号带宽内量化噪声功率,数字抽取滤波器对调制器输出信号进行滤波和降采样,将高速低精度的调制信号转换为低速高精度的数字信号。相比于Nyquist ADC,Sigma-Delta ADC能更好地满足低速高精度应用,并且对工艺变化的鲁棒性更强。MEMS(micro electronic and mechanical system)惯性器件接口电路中模数转换功能多采用Sigma-Delta转换,降低Sigma-Delta调制器功耗有助于控制MEMS惯性器件工作温度,提高器件工作稳定性。随着移动电子设备的发展,电池续航能力日益重要,降低Sigma-Delta调制器功耗有助于延长电池使用寿命。在如生物医疗先进领域的应用中,器件微型化也对功耗提出更苛刻的要求。因此Sigma-Delta调制器的低功耗设计有着很重要的现实意义。本文分析了Sigma-Delta调制器基本原理,晶体管电路实现中非理想特性对调制器性能的影响,完成了四阶前馈结构Sigma-Delta调制器的系统级设计和仿真,对Sigma-Delta调制器的低功耗设计进行了理论研究,从系统结构和电路结构出发优化调制器整体功耗,分析对比了动态偏置、开关运放、双采样等低功耗技术,确定了应用双采样技术的调制器方案,并基于CSMC 0.5μm工艺完成了调制器电路设计、版图设计和仿真。所设计的Sigma-Delta调制器满足输入信号带宽100k Hz,采样频率20MHz,由于采用了双采样方案,时钟频率为10MHz,电路仿真结果表明调制器SNR为99.6d B,三次谐波失真为-110.1d B,整体功耗约为8.1m W,FOM(figure of merit)达到170.5d B。
[Abstract]:Depending on the sampling frequency. Analog-to-digital converters are classified as Nyquist ADC and Sigma-Delta ADC. Sigma-Delta. ADC is composed of modulator and digital decimation filter. The modulator uses over-sampling technique and noise shaping technology to reduce the quantized noise power in the signal bandwidth. Digital decimation filter filters and demultiplexes the modulator output signal. The modulation signal with high speed and low precision can be converted into digital signal with low speed and high precision. Compared with Nyquist ADC Sigma-Delta ADC, it can better meet the requirements of low speed and high precision applications. And more robust to process change. MEMS micro electronic and mechanical system). In the interface circuit of inertial device, the conversion function of A / D is mostly Sigma-Delta conversion. Reducing the power consumption of Sigma-Delta modulator is helpful to control the operating temperature of MEMS inertial device and improve the stability of the device. With the development of mobile electronic equipment, the battery life ability becomes more and more important. Reducing the power consumption of Sigma-Delta modulators can help prolong the battery life, such as in advanced biomedical applications. The miniaturization of devices also puts forward more stringent requirements for power consumption. Therefore, the low power design of Sigma-Delta modulator is of great practical significance. This paper analyzes the Sigma-Delta modulator. Basic principles. The effect of non-ideal characteristics of transistor circuit on the performance of modulator is achieved. The system-level design and simulation of four-order feedforward structure Sigma-Delta modulator are completed. The low power design of Sigma-Delta modulator is studied theoretically. The overall power consumption of modulator is optimized from the system structure and circuit structure, and the dynamic bias and switching operational amplifier are analyzed and compared. The modulator scheme based on dual-sampling technology is determined, and the modulator circuit is designed based on CSMC 0.5 渭 m technology. Layout design and simulation. The designed Sigma-Delta modulator meets the input signal bandwidth of 100kHz and the sampling frequency of 20MHz. The clock frequency is 10MHz. The circuit simulation results show that the modulator SNR is 99.6dB, the third harmonic distortion is -110.1dB, and the overall power consumption is about 8.1m W. The FOM(figure of merit was 170.5 dB.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN761

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