8位20KSPS 0.4V超低功耗SAR ADC的研究

发布时间：2018-01-13 06:20

本文关键词：8位20KSPS 0.4V超低功耗SAR ADC的研究　出处：《西安电子科技大学》2015年硕士论文　论文类型：学位论文

【摘要】：逐次逼近型模数转换器(SAR ADC)是一种具有中等采样速度和中等转换精度的ADC,它具有结构简单,面积小,成本低廉,能耗低等优点,广泛运用于无线传感网络,便携式设备,医疗电子,精密仪器仪表等等场合。随着工艺技术的进步,工艺尺寸进一步缩小,给数字电路设计带来了飞速的发展,对于模数转换器,特别是SAR ADC,由于SAR ADC中,模拟电路模块比较少,所以更为适应工艺的进步,工艺的进步给SAR ADC带了飞跃发展。近年来,SAR ADC凭借着其独特的性能优势,越来越受到国内外广泛的科研团体的青睐,高速高精度低功耗SAR ADC的设计取得了显著成果,涌现出一系列性能优异的芯片设计。本文设计了一款8位20KSPS 0.4V超低功耗SAR ADC。通过对已有的各种关于电荷再分配结构时序的研究,提出了一种新型节能的电容开关时序,该结构巧妙的运用了整体切换的方式,极大的降低了时序切换过程中的转换能量。通过对几种不同时序开关的MATLAB建模仿真分析,与传统的开关时序对比,新型开关时序可以将电容的功耗和面积分别节省99.9%和75%。由于电容转换网络所消耗的能耗占整个系统的比重最大,因此,采用新型开关时序,能够非常有效的降低整个系统的能耗。由于系统电源电压比较低,采用一级栅压自举电路无法使得MOS管完全导通,给系统引入了极大的非线性,因此,本文采用了二级栅压自举结构。低压低速情况下,电荷泄漏情况比较严重,为了减小电荷泄漏所带来的误差,在ADC系统的逻辑结构中使用了可再生锁存的方式。在版图设计中,将模拟电路和数字电路之间设计一定的物理隔离,并且添加保护环,提高了系统的抗干扰能力。部分MOS管采用了双阱工艺,抑制闩锁效应。对电路各个模块版图采用了对称共质心布局,并且电容阵列周围加入陪衬电容,以提高整个电容阵列的匹配性。在比较器两个输入对管周围加入dummy管,以减小失配的影响。本文设计基于SMIC0.18μm CMOS工艺,完成版图设计后,整体芯片面积为1070×1240?m2。在0.4V电源电压下,20KSPS采样率下,本论文所设计的超低功耗SAR ADC的ENOB为7.98bit,SNDR为49.799dB,SFDR为73.83dB,THD为69.55dB,功耗为19.76nW,功耗的优值FOM为3.86fJ/conversion-step。
[Abstract]:Successive approximation analog-to-digital converter (ADCA / D) is a kind of ADCs with moderate sampling speed and medium conversion accuracy. It has the advantages of simple structure, small area, low cost and low energy consumption. It is widely used in wireless sensor networks, portable devices, medical electronics, precision instruments and other occasions. With the progress of technology, the process size is further reduced, which brings rapid development to the design of digital circuits. For analog-to-digital converters, especially SAR ADC, because of the small number of analog circuit modules in SAR ADC, it is more suitable for the progress of technology. The progress of technology has brought a great development to SAR ADC. In recent years, SAR ADC has been more and more popular with a wide range of scientific research organizations at home and abroad because of its unique performance advantages. The design of high speed, high precision and low power SAR ADC has achieved remarkable results. A series of excellent chip designs have emerged. An 8-bit 20KSPS 0.4V ultra-low power SAR is designed in this paper. ADC. through the existing research on the time series of charge redistribution structure. In this paper, a new type of energy saving capacitor switch timing is proposed, which makes use of the whole switching mode skillfully. It greatly reduces the switching energy in the process of timing switching. Through modeling and simulation analysis of several different timing switches, compared with the traditional switch timing. The new switching sequence can save the power consumption and area of the capacitor by 99.9% and 75, respectively. Because the energy consumption of the capacitive switching network is the largest in the whole system, the new switch timing is adopted. It can reduce the energy consumption of the whole system very effectively. Because the power supply voltage of the system is relatively low, the MOS transistor can not be completely switched on by using the first stage gate voltage bootstrap circuit, which brings a great deal of nonlinearity to the system. In this paper, the two-stage gate voltage bootstrap structure is used. At low voltage and low speed, the charge leakage is serious, in order to reduce the error caused by charge leakage. In the logical structure of ADC system, the method of renewable latch is used. In the layout design, the physical isolation between analog circuit and digital circuit is designed, and the protection ring is added. The anti-interference ability of the system is improved. Some MOS transistors adopt double well technology to suppress latch effect. The layout of each module adopts symmetrical co-centroid layout and the capacitor array is surrounded by a foil capacitor. In order to improve the matching performance of the whole capacitor array, the dummy tube is added around the comparator's two inputs to reduce the mismatch. The design of this paper is based on the SMIC0.18 渭 m CMOS process. After layout design, the overall chip area is 1070 脳 1240? At the sampling rate of 20KSPS at 0.4V power supply, the ENOB of the ultra-low power SAR ADC designed in this paper is 7.98bit. The SNDR was 49.799dBU SFDR (73.83dBN) and the power consumption was 19.76nW. The FOM of power consumption is 3.86fJ / conversion-step.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792

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