规整电路的半自动物理实现与优化

发布时间：2018-01-19 03:10

本文关键词： 规整电路位片数据通路交叉开关半自动　出处：《国防科学技术大学》2015年硕士论文　论文类型：学位论文

【摘要】：EDA自动化工具的不断进步,大大缩短了集成电路的设计周期,其布局与优化算法对随机逻辑功能块具有很好的物理实现与优化效果,但对于复杂性较高的规整结构,EDA工具不能高效的利用电路内部规整性去实现高性能设计的时序收敛。针对上述问题,本文总结和优化了对规整电路物理设计具有良好优化效果的半自动物理实现方法。半自动物理实现方法的优势在于可以借助脚本来快速实现规整电路的手工布局,利用布局的规整性来引导工具自动布线,提高规整电路的性能。首先,从RTL代码中挖掘出电路内部存在的规整性,用能够体现规整性的最小可重复单元组合成规整电路的电路图,以手工搭建电路的方式代替工具自动综合,提取包含电路规整信息的门级网表。其次,根据电路的布图规划约束,确定最小可重复单元的布局形状与在物理视图中的绝对位置,精确计算出可重复单元间的相对间距,借助脚本将最小可重复单元的手工部局信息复制到其它可重复单元之中,快速完成规整单元的手工布局。最后,让规整的布局来引导工具自动布线,高效地实现电路的物理设计。根据电路结构的不同可以将规整结构分为位片式一维规整结构和二维阵列规整结构。数据通路常常组织成位片式结构。位片式结构中所有数据位的结构完全相同或相似,设计者只需实现一位的手工布局,然后将该位的物理信息重复调用,快速构建出整给数据通路的手工布局。本文以数据通路中地址部件为实验载体,利用半自动物理实现方法将数据通路中的规整性运用于物理实现,使得地址部件的功耗降低了3.62%,延时最大减少10.34%。二维阵列规整结构通常存在于大量数据交换通路之中。交叉开关网络需要译码阵列与选择阵列的协同合作才能完成交叉开关的功能,具有典型的二维规整阵列。EDA自动布局算法不能很好地处理复杂的逻辑阵列。半自动物理实现方式可以提取二维阵列中的最小可重复单元,然后以它的布局信息为模板,借助脚本快速实现整个二维阵列规整的手工布局。本文选取具有规整结构的交叉开关网络作为二维阵列规整结构的实现载体,将这种阵列规整性充分地运用到物理实现过程中,使功耗降低了26.37%,延时最大减少了25.1%。在高性能芯片设计过程中,设计者可以应用这种方法优化芯片内的规整电路,以协助芯片整体的优化工作。
[Abstract]:With the continuous progress of EDA automation tools, the design cycle of integrated circuits is greatly shortened. The layout and optimization algorithms have good physical realization and optimization effect for random logic function blocks. However, EDA tools with high complexity can not efficiently utilize the internal regularity of the circuit to achieve the timing convergence of high performance design. This paper summarizes and optimizes the semi-automatic physical realization method which has good optimization effect on the physical design of regular circuit. The advantage of semi-automatic physical realization method is that the manual layout of regular circuit can be realized quickly by means of script. . Using the layout regularity to guide the tool automatic routing, improve the performance of the structured circuit. Firstly, the internal regularity of the circuit is mined from the RTL code. The circuit diagram is composed of the least repeatable unit which can reflect the regularity of the circuit. Instead of the tool, the circuit is automatically synthesized by manual construction, and the gate network table which contains the information of circuit regularity is extracted. Secondly. According to the layout planning constraints of the circuit, the layout shape of the minimum repeatable cell and the absolute position in the physical view are determined, and the relative distance between the repeatable elements is calculated accurately. With the help of the script, the manual information of the smallest repeatable unit is copied to other repeatable units, and the manual layout of the regular unit is completed quickly. Finally, let the regular layout to guide the tool automatic routing. The physical design of the circuit can be realized efficiently. According to the different circuit structure, the structured structure can be divided into one dimensional structure and two dimensional array structure. The data path is often organized into a bit-chip structure. The structure of all data bits in the. The designer only need to realize the manual layout of one bit, then repeat the physical information of the bit, and quickly construct the manual layout of the integrated data path. In this paper, the address part of the data path is used as the experimental carrier. By using semi-automatic physical implementation method, the regularity in the data path is applied to the physical implementation, and the power consumption of the address component is reduced by 3.62%. The maximum delay is reduced by 10.34. The two-dimensional array regularization structure usually exists in a large number of data exchange paths. The cross-switch network needs the cooperative cooperation of decoding array and selecting array to complete the function of crossover switch. . A typical two-dimensional structured array. EDA automatic layout algorithm can not deal with complex logical arrays. Semi-automatic physical implementation can extract the smallest repeatable elements in two-dimensional arrays. Then the layout information is used as template, and the manual layout of the whole two-dimensional array is realized quickly by means of script. In this paper, the cross-switch network with regular structure is selected as the implementation carrier of two-dimensional array warping structure. The array regularity is fully applied to the physical implementation process, the power consumption is reduced by 26.37, the delay is reduced by 25.1. in the process of high performance chip design. This method can be used to optimize the structured circuits in the chip to assist the overall optimization of the chip.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN40

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