应用基于双权值的门替换方法缓解电路老化

发布时间：2018-01-20 05:56

本文关键词： 负偏置温度不稳定性电路时序违规双权值关键门非门替换　出处：《应用科学学报》2017年02期 　论文类型：期刊论文

【摘要】：在纳米工艺水平下,负偏置温度不稳定性(negative bias temperature instability,NBTI)成为影响集成电路可靠性的关键性因素.NBTI效应导致晶体管阈值电压增加,老化加剧,最终使电路时序违规.为了缓解电路的NBTI效应,定义了时延关键性权值和拓扑结构关键性权值.使用该双权值识别的关键门更加精确,并且考虑到了关键门的扇入门为非门的情况,即将非门视为单输入与非门,并将其替换为双输入与非门,从而能更加全面地防护关键门.应用基于双权值的门替换方法对基于45 nm晶体管工艺的ISCAS85基准电路实验结果显示:当电路时序余量为5%时,不考虑非门替换时电路的时延改善率为38.29%,考虑非门替换时电路的时延改善率为60.66%.
[Abstract]:At the nanometer process level, the negative bias temperature instability is negative bias temperature instability. NBTI) has become a key factor affecting the reliability of integrated circuits. NBTI effect leads to the increase of transistor threshold voltage, aggravation of aging, and ultimately the circuit timing violation. In order to alleviate the NBTI effect of the circuit. The delay critical weight and the topology critical weight are defined. The key gates identified by the double weights are more accurate and take into account the fact that the key gate's entry is a non-gate. Treat non-gate as single-input and non-gate, and replace it with double-input and non-gate. Thus, the key gates can be protected more comprehensively. The experimental results of ISCAS85 reference circuit based on 45nm transistor process show that: (1) the gate substitution method based on double weights is applied to the experimental results of the ISCAS85 reference circuit based on 45 nm transistor process. When the circuit timing allowance is 5. The delay improvement rate is 38.29 when non-gate substitution is not considered, and 60.66 when non-gate substitution is considered.
【作者单位】：合肥工业大学电子科学与应用物理学院;
【基金】：国家自然科学基金(No.61371025,No.61274036)资助
【分类号】：TN40
【正文快照】： 随着集成电路制造工艺的不断发展,器件工艺尺寸不断减小,晶体管老化成为影响集成电路可靠性的重要问题,其中负偏置温度不稳性(negative bias temperature instability,NBTI)效应是最主要的老化机制.NBTI效应主要影响电路中的PMOS晶体管,当PMOS晶体管处于受压状态,即PMOS晶体管

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