功率VDMOSFET终端结构的击穿特性研究与设计

发布时间：2018-01-25 20:48

本文关键词： VDMOSFET 击穿电压最大表面电场峰值场限环场板终端面积　出处：《西南交通大学》2015年硕士论文　论文类型：学位论文

【摘要】：本论文主要研究内容为功率VDMOSFET终端结构的击穿特性。对一款700VVDMOSFET终端结构进行了优化设计。首先研究了半导体功率器件雪崩击穿的条件和机制,代入无限大平面结和突变柱状结的边界条件得到击穿电压的解析方程。通过对无限大平面结的研究,发现平面结与外延层参数的选取有直接关系,因此可以推导计算出外延层浓度和厚度参数,通过仿真验证,计算出来的外延层参数与实际的仿真结果误差很小。突变柱状结主要用于主结击穿电压的研究,结果表明柱状结的曲率半径与结的击穿电压有直接关系,曲率越小,结的击穿电压越高,这也为其他终端技术提供了理论基础。然后介绍了几种常见的终端技术,对横向变掺杂技术做了简要分析,对场限环技术,终端场板技术做了详细分析和仿真验证。通过改变场限环结深,场限环间距,复合场板结构,探究其与终端击穿特性之间的关系。之后提出了一种高压功率器件改进场板的方法与设计,通过调节金属-多晶硅复合场板结构,使金属浮空场板的边缘覆盖住多晶硅浮空场板的边缘,最终使场板内部的场强相互削弱,减小表面最大电场。基于此理论,做了一组采用传统金属-多晶硅复合场板和改进后的金属-多晶硅复合场板结构的VDMOSFET终端仿真验证。通过上文对终端技术的研究,本文设计了一款4个场限环外加金属多晶硅复合场板结构的VDMOSFET,通过对外延层参数的优化,场限环位置和个数的选取,金属-多晶硅复合场板参数的调节,最终在151μm的有效终端长度上设计了一款耐压为772V的终端结构,在保证相同耐压前提下比其他文献中的同类终端节约芯片面积26%。
[Abstract]:In this thesis, the breakdown characteristics of power VDMOSFET terminal structure are studied. A 700V DMOSFET terminal structure is optimized. Firstly, the semiconductor power device Xue is studied. The condition and mechanism of avalanche breakdown. The analytical equation of breakdown voltage is obtained by inserting boundary conditions of infinite plane junction and abrupt cylindrical junction. Through the study of infinite plane junction, it is found that the plane junction is directly related to the selection of the parameters of the epitaxial layer. Therefore, the parameters of the concentration and thickness of the epitaxial layer can be deduced and calculated. Through simulation, the error between the calculated parameters and the actual simulation results is very small. The abrupt columnar junction is mainly used to study the breakdown voltage of the main junction. The results show that the curvature radius of the cylindrical junction is directly related to the breakdown voltage of the junction. The smaller the curvature, the higher the breakdown voltage of the junction. This also provides a theoretical basis for other terminal technologies. Then several common terminal technologies are introduced. The transverse variable doping technology is briefly analyzed and the field limiting ring technology is analyzed. The terminal field plate technology is analyzed in detail and verified by simulation. By changing the depth of the field limiting ring the distance between the field limiting rings and the composite field plate structure. After exploring the relationship between the breakdown characteristics and the terminal breakdown characteristics, a method and design of improving the field plate of high voltage power device is proposed, and the structure of metal-polycrystalline silicon composite field plate is adjusted. The edge of the metal floating field plate is covered with the edge of the polysilicon floating field plate, and finally the field intensity inside the plate is weakened and the maximum surface electric field is reduced. A group of VDMOSFET terminals with traditional metal-polysilicon composite field board and improved metal-polycrystalline silicon composite field board structure are simulated and verified. Through the research of terminal technology above. In this paper, a VDMOSFETs with four field limiting rings and metal polysilicon composite structure are designed. By optimizing the parameters of the epitaxial layer, the position and the number of the field limiting rings are selected. By adjusting the parameters of metal-polysilicon composite field plate, a terminal structure with a voltage of 772V has been designed on the effective terminal length of 151 渭 m. On the premise of the same voltage, the chip area is saved by 26% compared with the similar terminals in other literatures.
【学位授予单位】：西南交通大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN386

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