针对数字集成电路抗辐射加固结构的研究

发布时间：2018-01-28 11:43

本文关键词： 软错误单粒子效应锁存器工艺偏差门控时钟　出处：《合肥工业大学》2015年硕士论文　论文类型：学位论文

【摘要】：随着集成电路工艺尺寸的不断降低,电路对空间辐射引起的单粒子效应越来越敏感。尤其是当集成电路应用在航空航天领域时,单粒子效应已经成为导致电路失效的主要原因之一。国内外学者为此做出了大量的研究并提出很多抗辐射加固的电路结构。但是这些结构大多只能容忍SEU或SET,而且通常面临着面积、功耗和延迟开销较大的问题。基于上述问题,本文做了如下工作：阐述了辐射以及辐射引起的单粒子效应,并重点介绍了单粒子瞬态和单粒子翻转,分析了其产生机理和对电路的影响。之后列举了现有的抗辐射加固技术,并且比较了这些技术的优缺点。针对现有加固技术无法同时防护SEU和SET以及受工艺偏差影响较大的问题,提出一种高可靠的容软错误锁存器HLTL。该锁存器采用分离反相器P、N管栅极的方法构建内部冗余存储节点使其对SEU完全免疫,并且进行了滤波设计使其可以屏蔽SET。 HSPICE的仿真结果表明,与其它加固结构相比,该锁存器在综合考虑容错性能和开销时有明显的优势,而且受到工艺偏差和温度的影响较小。针对现有加固电路功耗较高的问题,本文基于时间和空间冗余技术提出了一种低开销的容软错误锁存器DSH-CG。该锁存器包括两个内部冗余模块和一个由C单元与保持器组成的输出级,不但可以过滤上游组合逻辑传播过来的SET脉冲,而且对SEU完全免疫。SPICE仿真结果表明,与同类锁存器相比,该锁存器的功耗开销较小而且可以应用于门控时钟电路。
[Abstract]:With the decreasing of IC process size, the circuit is more and more sensitive to the single particle effect caused by space radiation, especially when the integrated circuit is applied in the field of aerospace. Single particle effect has become one of the main causes of circuit failure. Scholars at home and abroad have made a lot of research and proposed a lot of radiation resistant circuit structures. However, most of these structures can only tolerate SEU or. SET. And usually face the problem of large area, power consumption and delay overhead. Based on the above problems, this paper has done the following work: the radiation and radiation induced by single particle effect. The single particle transient and single particle flipping are introduced, and the mechanism and the influence on the circuit are analyzed. Then, the existing anti-radiation reinforcement techniques are listed. The advantages and disadvantages of these technologies are compared. The existing reinforcement technology can not protect SEU and SET at the same time and is greatly affected by the process deviation. A highly reliable soft-error-tolerant latch, HLTL, is proposed. The latch uses the method of separating the inverters to construct the internal redundant storage nodes to be completely immune to SEU. The simulation results show that compared with other strengthened structures, this latch has obvious advantages when considering the fault tolerance performance and overhead. Moreover, it is less affected by process deviation and temperature, aiming at the problem of high power consumption of existing strengthened circuits. This paper presents a low overhead soft-error tolerant latch DSH-CG based on temporal and spatial redundancy. The latch consists of two internal redundant modules and an output stage composed of C unit and holder. Not only the SET pulse propagated by the upstream combinational logic can be filtered, but also the simulation results of SEU complete immunity. Spice show that compared with the similar latch. The latch has low power consumption and can be used in gated clock circuits.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN431.2

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