锁相频率合成电路仿真分析及设计实现

发布时间：2018-01-29 05:03

本文关键词： 锁相环环路带宽捕获时间相位噪声最佳环路带宽　出处：《中国科学院研究生院(空间科学与应用研究中心)》2015年硕士论文　论文类型：学位论文

【摘要】：随着科学技术的发展与进步,锁相环作为一个相位自动反馈系统,以其窄带跟踪、控制无频差、低门限、抗干扰能力强以及易于集成化等诸多优点,在电子相关的多个领域得到了极其广泛的应用。在锁相环的设计过程中,环路带宽的选择是整个设计成功与否的重要一环。一方面,环路带宽的选取会影响环路捕获带和捕获时间,即环路的捕获性能;另一方面,环路输出相位噪声的大小不仅与环路各器件噪声特性有关,其在很大程度上依赖于环路带宽的选取。因此,本文针对环路带宽与环路捕获性能的关系、环路带宽对环路输出相位噪声的影响进行了深入的探讨与研究。第一章,着重介绍锁相技术发展历史、应用领域及发展现状;第二章,从锁相环基本原理入手,从理论上分析了简单二阶锁相环环路带宽和环路捕获性能的关系以及环路输出相位噪声模型;第三章,利用ADS电路仿真软件,搭建基于不同类型环路滤波器的锁相环电路模型,并对其分别进行时域仿真和频域仿真来验证理论分析;第四章,基于PE3236锁相环PLL芯片,完成了一款高性能锁相频率合成电路的设计;第五章,对锁相频率合成电路进行调试和测试,通过调节电路参数改变环路带宽,测试不同环路带宽条件下环路捕获时间和输出相位噪声,测试结果与理论分析基本吻合。
[Abstract]:With the development and progress of science and technology, PLL, as a phase automatic feedback system, has many advantages, such as narrow band tracking, no frequency difference control, low threshold, strong anti-jamming ability and easy integration. In the design process of PLL, the choice of loop bandwidth is an important link for the success of the whole design. The selection of loop bandwidth will affect the capture band and time of the loop, that is, the performance of the loop. On the other hand, the output phase noise of the loop is not only related to the noise characteristics of the loop devices, but also depends on the selection of the loop bandwidth to a great extent. In this paper, the relationship between loop bandwidth and the performance of loop acquisition is discussed. The influence of loop bandwidth on loop output phase noise is discussed. Chapter 1 focuses on the history of phase-locked technology. Application field and development status; In the second chapter, starting with the basic principle of PLL, the relationship between the bandwidth of the simple second-order PLL loop and the performance of the loop acquisition and the output phase noise model of the loop are analyzed theoretically. In chapter 3, using the ADS circuit simulation software, the phase-locked loop circuit model based on different types of loop filter is built, and the time domain simulation and frequency domain simulation are carried out to verify the theoretical analysis. In chapter 4th, based on PE3236 PLL PLL chip, a high performance PLL frequency synthesizer is designed. In Chapter 5th, the phase-locked frequency synthesizer is debugged and tested. By adjusting the circuit parameters, the loop bandwidth is changed to test the loop acquisition time and the output phase noise under different loop bandwidth conditions. The test results are in good agreement with the theoretical analysis.
【学位授予单位】：中国科学院研究生院(空间科学与应用研究中心)
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN74

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