基于CMOS工艺的低噪声锁相环的研究与设计

发布时间：2018-02-01 15:49

本文关键词： 锁相环低噪声 RFID 亚采样死区　出处：《中国科学技术大学》2017年硕士论文　论文类型：学位论文

【摘要】：随着无线通信技术的飞速发展,移动终端设备的需求不断增加,WiFi,Bluetooth,RFID等短距离无线通信协议被广泛的开发利用。所有的通信系统都需要一个稳定的时钟,基于锁相环(PLL)的频率合成器是无线收发机中的重要组成部分,为系统提供本振信号。时钟的精度影响着系统的整体性能,因此一个低噪声的时钟信号源是高性能无线收发机中必不可少的。本文的目标是设计实现低噪声的锁相环。首先介绍了锁相环及其各组成模块的基本原理、电路结构及非理想效应;随后分析了环路带宽和相位裕度对锁相环稳定性的影响;最后基于连续时间线性相位域模型,分析了其相位噪声性能。本文设计了一款应用于超高频RFID阅读器的锁相环电路。锁相环输出频率为840 MHz-960 MHz,符合国际工不同地区的超高频RF1D协议标准。考虑协议对锁定时间和相位噪声性能的要求,本文选取环路带宽为40KHz。设计采用0.13 μm CMOS工艺,仿真结果显示,压控振荡器输出频率为1.6 GHz-2.0 GHz,VCO在偏离载波频率100 KHz处的相位噪声为-112 dBc/Hz。锁相环的锁定时间为100μs,频偏100 KHz和1 MHz处相位噪声分别为-106 dBc/Hz和-128 dBc/Hz。本文设计了可以快速锁定的低噪声亚采样锁相环。在亚采样锁相环锁定状态下分频器不参与环路工作,因此减少了分频器所贡献的噪声。另外,由亚采样鉴相器和亚采样电荷泵所贡献的噪声不会被放大N2倍,从而极大程度地减小了锁相环的带内噪声。采用对称式的采样器可以改善由VCO负载不匹配引入的参考杂散。为了缩短亚采样锁相环的锁定时间,本文提出了可调节死区阈值的鉴频鉴相器,对其进行了理论分析,并与传统固定死区阈值的鉴频鉴相器进行了对比。设计采用0.18μm CMOS工艺,仿真结果显示,锁相环锁定时间为3μs,参考杂散为-79.81 dBc。在偏移载波频率200 KHz处,锁相环带内噪声为-124dBc/Hz。
[Abstract]:With the rapid development of wireless communication technology, the demand of mobile terminal equipment is increasing. Short-range wireless communication protocols such as RFID are widely used. All communication systems need a stable clock. The frequency synthesizer based on PLL (PLL) is an important part of wireless transceiver, which provides the local oscillator signal for the system. The precision of clock affects the overall performance of the system. Therefore, a low noise clock signal source is essential in high performance wireless transceiver. The goal of this paper is to design and implement low noise PLL. Firstly, the basic principle of PLL and its components are introduced. Circuit structure and non-ideal effect; Then the influence of loop bandwidth and phase margin on the stability of PLL is analyzed. Finally, it is based on continuous time linear phase domain model. The phase noise performance is analyzed. A PLL circuit for UHF RFID reader is designed. The output frequency of PLL is 840 MHz-960 MHz. Meet the UHF RF1D protocol standards in different parts of the international industry. Consider the requirements of the protocol for locking time and phase noise performance. In this paper, the loop bandwidth of 40kHz is chosen. The design adopts 0.13 渭 m CMOS process. The simulation results show that the output frequency of the VCO is 1.6 GHz-2.0 GHz. The phase noise of VCO is -112dBc / Hz. the locking time of PLL is 100 渭 s. The phase noise at 100 KHz and 1 MHz frequency offset is -106 dBc/Hz and -128, respectively. In this paper, we design a low-noise sub-sampling phase-locked loop which can be locked quickly. The frequency divider does not participate in the loop operation under the sub-sampling phase-locked state. Thus, the noise contributed by the frequency divider is reduced. In addition, the noise contributed by the subsampling phase discriminator and the subsampling charge pump is not amplified by N2 times. Therefore, the in-band noise of PLL is greatly reduced. The reference spurious introduced by VCO load mismatch can be improved by using symmetrical sampler. In order to shorten the locking time of sub-sampling PLL. In this paper, a phase discriminator with adjustable dead-zone threshold is proposed and analyzed theoretically, and compared with that of traditional fixed-dead-zone threshold. The design adopts 0.18 渭 m CMOS process. The simulation results show that the locking time of PLL is 3 渭 s and the reference spurious is -79.81 dBc. At the offset carrier frequency of 200 KHz, the in-band noise of PLL is -124dBc / Hz.
【学位授予单位】：中国科学技术大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN386;TP391.44

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